e1000: Support for 82571 and 82572 controllers (868d5309) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/net/e1000/e1000_ethtool.c

+8 −1

Original line number	Diff line number	Diff line
		@@ -696,6 +696,11 @@ e1000_reg_test(struct e1000_adapter adapter, uint64_t data)
		* Some bits that get toggled are ignored.
		*/
		switch (adapter->hw.mac_type) {
		/* there are several bits on newer hardware that are r/w */
		case e1000_82571:
		case e1000_82572:
		toggle = 0x7FFFF3FF;
		break;
		case e1000_82573:
		toggle = 0x7FFFF033;
		break;
		@@ -1245,6 +1250,8 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
		case e1000_82541_rev_2:
		case e1000_82547:
		case e1000_82547_rev_2:
		case e1000_82571:
		case e1000_82572:
		case e1000_82573:
		return e1000_integrated_phy_loopback(adapter);
		break;
		@@ -1625,7 +1632,7 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
		if(!data \|\| data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
		data = (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ);

		if(adapter->hw.mac_type < e1000_82573) {
		if(adapter->hw.mac_type < e1000_82571) {
		if(!adapter->blink_timer.function) {
		init_timer(&adapter->blink_timer);
		adapter->blink_timer.function = e1000_led_blink_callback;

drivers/net/e1000/e1000_hw.c

+186 −33

Original line number	Diff line number	Diff line
		@@ -83,14 +83,14 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =

		static const
		uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
		{ 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
		22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
		32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
		43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
		57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
		73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
		91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
		108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
		{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
		0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
		6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
		21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
		40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
		60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
		83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
		104, 109, 114, 118, 121, 124};


		/******************************************************************************
		@@ -286,7 +286,6 @@ e1000_set_mac_type(struct e1000_hw *hw)
		case E1000_DEV_ID_82546GB_FIBER:
		case E1000_DEV_ID_82546GB_SERDES:
		case E1000_DEV_ID_82546GB_PCIE:
		case E1000_DEV_ID_82546GB_QUAD_COPPER:
		hw->mac_type = e1000_82546_rev_3;
		break;
		case E1000_DEV_ID_82541EI:
		@@ -305,8 +304,19 @@ e1000_set_mac_type(struct e1000_hw *hw)
		case E1000_DEV_ID_82547GI:
		hw->mac_type = e1000_82547_rev_2;
		break;
		case E1000_DEV_ID_82571EB_COPPER:
		case E1000_DEV_ID_82571EB_FIBER:
		case E1000_DEV_ID_82571EB_SERDES:
		hw->mac_type = e1000_82571;
		break;
		case E1000_DEV_ID_82572EI_COPPER:
		case E1000_DEV_ID_82572EI_FIBER:
		case E1000_DEV_ID_82572EI_SERDES:
		hw->mac_type = e1000_82572;
		break;
		case E1000_DEV_ID_82573E:
		case E1000_DEV_ID_82573E_IAMT:
		case E1000_DEV_ID_82573L:
		hw->mac_type = e1000_82573;
		break;
		default:
		@@ -315,6 +325,8 @@ e1000_set_mac_type(struct e1000_hw *hw)
		}

		switch(hw->mac_type) {
		case e1000_82571:
		case e1000_82572:
		case e1000_82573:
		hw->eeprom_semaphore_present = TRUE;
		/* fall through */
		@@ -351,6 +363,8 @@ e1000_set_media_type(struct e1000_hw *hw)
		switch (hw->device_id) {
		case E1000_DEV_ID_82545GM_SERDES:
		case E1000_DEV_ID_82546GB_SERDES:
		case E1000_DEV_ID_82571EB_SERDES:
		case E1000_DEV_ID_82572EI_SERDES:
		hw->media_type = e1000_media_type_internal_serdes;
		break;
		default:
		@@ -523,6 +537,8 @@ e1000_reset_hw(struct e1000_hw *hw)
		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
		E1000_WRITE_FLUSH(hw);
		/* fall through */
		case e1000_82571:
		case e1000_82572:
		ret_val = e1000_get_auto_rd_done(hw);
		if(ret_val)
		/* We don't want to continue accessing MAC registers. */
		@@ -683,6 +699,9 @@ e1000_init_hw(struct e1000_hw *hw)
		switch (hw->mac_type) {
		default:
		break;
		case e1000_82571:
		case e1000_82572:
		ctrl \|= (1 << 22);
		case e1000_82573:
		ctrl \|= E1000_TXDCTL_COUNT_DESC;
		break;
		@@ -694,6 +713,25 @@ e1000_init_hw(struct e1000_hw *hw)
		e1000_enable_tx_pkt_filtering(hw);
		}

		switch (hw->mac_type) {
		default:
		break;
		case e1000_82571:
		ctrl = E1000_READ_REG(hw, TXDCTL1);
		ctrl &= ~E1000_TXDCTL_WTHRESH;
		ctrl \|= E1000_TXDCTL_COUNT_DESC \| E1000_TXDCTL_FULL_TX_DESC_WB;
		ctrl \|= (1 << 22);
		E1000_WRITE_REG(hw, TXDCTL1, ctrl);
		break;
		}



		if (hw->mac_type == e1000_82573) {
		uint32_t gcr = E1000_READ_REG(hw, GCR);
		gcr \|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
		E1000_WRITE_REG(hw, GCR, gcr);
		}

		/* Clear all of the statistics registers (clear on read). It is
		* important that we do this after we have tried to establish link
		@@ -878,6 +916,14 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

		DEBUGFUNC("e1000_setup_fiber_serdes_link");

		/* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
		* until explicitly turned off or a power cycle is performed. A read to
		* the register does not indicate its status. Therefore, we ensure
		* loopback mode is disabled during initialization.
		*/
		if (hw->mac_type == e1000_82571 \|\| hw->mac_type == e1000_82572)
		E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);

		/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
		* set when the optics detect a signal. On older adapters, it will be
		* cleared when there is a signal. This applies to fiber media only.
		@@ -2943,6 +2989,8 @@ e1000_phy_reset(struct e1000_hw *hw)

		switch (hw->mac_type) {
		case e1000_82541_rev_2:
		case e1000_82571:
		case e1000_82572:
		ret_val = e1000_phy_hw_reset(hw);
		if(ret_val)
		return ret_val;
		@@ -2981,6 +3029,16 @@ e1000_detect_gig_phy(struct e1000_hw *hw)

		DEBUGFUNC("e1000_detect_gig_phy");

		/* The 82571 firmware may still be configuring the PHY. In this
		* case, we cannot access the PHY until the configuration is done. So
		* we explicitly set the PHY values. */
		if(hw->mac_type == e1000_82571 \|\|
		hw->mac_type == e1000_82572) {
		hw->phy_id = IGP01E1000_I_PHY_ID;
		hw->phy_type = e1000_phy_igp_2;
		return E1000_SUCCESS;
		}

		/* Read the PHY ID Registers to identify which PHY is onboard. */
		ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
		if(ret_val)
		@@ -3334,6 +3392,21 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
		eeprom->use_eerd = FALSE;
		eeprom->use_eewr = FALSE;
		break;
		case e1000_82571:
		case e1000_82572:
		eeprom->type = e1000_eeprom_spi;
		eeprom->opcode_bits = 8;
		eeprom->delay_usec = 1;
		if (eecd & E1000_EECD_ADDR_BITS) {
		eeprom->page_size = 32;
		eeprom->address_bits = 16;
		} else {
		eeprom->page_size = 8;
		eeprom->address_bits = 8;
		}
		eeprom->use_eerd = FALSE;
		eeprom->use_eewr = FALSE;
		break;
		case e1000_82573:
		eeprom->type = e1000_eeprom_spi;
		eeprom->opcode_bits = 8;
		@@ -3558,6 +3631,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
		eecd &= ~E1000_EECD_REQ;
		E1000_WRITE_REG(hw, EECD, eecd);
		DEBUGOUT("Could not acquire EEPROM grant\n");
		e1000_put_hw_eeprom_semaphore(hw);
		return -E1000_ERR_EEPROM;
		}
		}
		@@ -4064,7 +4138,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
		return -E1000_ERR_EEPROM;
		}

		/* 82573 reads only through eerd */
		/* 82573 writes only through eewr */
		if(eeprom->use_eewr == TRUE)
		return e1000_write_eeprom_eewr(hw, offset, words, data);

		@@ -4353,9 +4427,16 @@ e1000_read_mac_addr(struct e1000_hw * hw)
		hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
		hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
		}
		if(((hw->mac_type == e1000_82546) \|\| (hw->mac_type == e1000_82546_rev_3)) &&
		(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
		switch (hw->mac_type) {
		default:
		break;
		case e1000_82546:
		case e1000_82546_rev_3:
		case e1000_82571:
		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
		hw->perm_mac_addr[5] ^= 0x01;
		break;
		}

		for(i = 0; i < NODE_ADDRESS_SIZE; i++)
		hw->mac_addr[i] = hw->perm_mac_addr[i];
		@@ -4385,6 +4466,12 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
		e1000_rar_set(hw, hw->mac_addr, 0);

		rar_num = E1000_RAR_ENTRIES;

		/* Reserve a spot for the Locally Administered Address to work around
		* an 82571 issue in which a reset on one port will reload the MAC on
		* the other port. */
		if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
		rar_num -= 1;
		/* Zero out the other 15 receive addresses. */
		DEBUGOUT("Clearing RAR[1-15]\n");
		for(i = 1; i < rar_num; i++) {
		@@ -4427,6 +4514,12 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
		/* Clear RAR[1-15] */
		DEBUGOUT(" Clearing RAR[1-15]\n");
		num_rar_entry = E1000_RAR_ENTRIES;
		/* Reserve a spot for the Locally Administered Address to work around
		* an 82571 issue in which a reset on one port will reload the MAC on
		* the other port. */
		if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
		num_rar_entry -= 1;

		for(i = rar_used_count; i < num_rar_entry; i++) {
		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
		@@ -4984,7 +5077,6 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
		temp = E1000_READ_REG(hw, ICTXQEC);
		temp = E1000_READ_REG(hw, ICTXQMTC);
		temp = E1000_READ_REG(hw, ICRXDMTC);

		}

		/******************************************************************************
		@@ -5151,6 +5243,8 @@ e1000_get_bus_info(struct e1000_hw *hw)
		hw->bus_speed = e1000_bus_speed_unknown;
		hw->bus_width = e1000_bus_width_unknown;
		break;
		case e1000_82571:
		case e1000_82572:
		case e1000_82573:
		hw->bus_type = e1000_bus_type_pci_express;
		hw->bus_speed = e1000_bus_speed_2500;
		@@ -5250,6 +5344,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
		int32_t ret_val;
		uint16_t agc_value = 0;
		uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
		uint16_t max_agc = 0;
		uint16_t i, phy_data;
		uint16_t cable_length;

		@@ -5338,6 +5433,40 @@ e1000_get_cable_length(struct e1000_hw *hw,
		IGP01E1000_AGC_RANGE) : 0;
		*max_length = e1000_igp_cable_length_table[agc_value] +
		IGP01E1000_AGC_RANGE;
		} else if (hw->phy_type == e1000_phy_igp_2) {
		uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
		{IGP02E1000_PHY_AGC_A,
		IGP02E1000_PHY_AGC_B,
		IGP02E1000_PHY_AGC_C,
		IGP02E1000_PHY_AGC_D};
		/* Read the AGC registers for all channels */
		for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
		ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
		if (ret_val)
		return ret_val;

		/* Getting bits 15:9, which represent the combination of course and
		* fine gain values. The result is a number that can be put into
		* the lookup table to obtain the approximate cable length. */
		cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
		IGP02E1000_AGC_LENGTH_MASK;

		/* Remove min & max AGC values from calculation. */
		if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc])
		min_agc = cur_agc;
		if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc])
		max_agc = cur_agc;

		agc_value += e1000_igp_2_cable_length_table[cur_agc];
		}

		agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]);
		agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);

		/* Calculate cable length with the error range of +/- 10 meters. */
		*min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
		(agc_value - IGP02E1000_AGC_RANGE) : 0;
		*max_length = agc_value + IGP02E1000_AGC_RANGE;
		}

		return E1000_SUCCESS;
		@@ -6465,6 +6594,8 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
		default:
		msec_delay(5);
		break;
		case e1000_82571:
		case e1000_82572:
		case e1000_82573:
		while(timeout) {
		if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
		@@ -6494,10 +6625,31 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
		int32_t
		e1000_get_phy_cfg_done(struct e1000_hw *hw)
		{
		int32_t timeout = PHY_CFG_TIMEOUT;
		uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;

		DEBUGFUNC("e1000_get_phy_cfg_done");

		/* Simply wait for 10ms */
		switch (hw->mac_type) {
		default:
		msec_delay(10);
		break;
		case e1000_82571:
		case e1000_82572:
		while (timeout) {
		if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
		break;
		else
		msec_delay(1);
		timeout--;
		}

		if (!timeout) {
		DEBUGOUT("MNG configuration cycle has not completed.\n");
		return -E1000_ERR_RESET;
		}
		break;
		}

		return E1000_SUCCESS;
		}
		@@ -6569,8 +6721,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
		return;

		swsm = E1000_READ_REG(hw, SWSM);
		/* Release both semaphores. */
		swsm &= ~(E1000_SWSM_SMBI \| E1000_SWSM_SWESMBI);
		swsm &= ~(E1000_SWSM_SWESMBI);
		E1000_WRITE_REG(hw, SWSM, swsm);
		}

		@@ -6606,6 +6757,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
		* if this is the case. We read FWSM to determine the manageability mode.
		*/
		switch (hw->mac_type) {
		case e1000_82571:
		case e1000_82572:
		case e1000_82573:
		fwsm = E1000_READ_REG(hw, FWSM);
		if((fwsm & E1000_FWSM_MODE_MASK) != 0)

drivers/net/e1000/e1000_hw.h

+84 −12

Original line number	Diff line number	Diff line
		@@ -57,6 +57,8 @@ typedef enum {
		e1000_82541_rev_2,
		e1000_82547,
		e1000_82547_rev_2,
		e1000_82571,
		e1000_82572,
		e1000_82573,
		e1000_num_macs
		} e1000_mac_type;
		@@ -478,10 +480,16 @@ uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
		#define E1000_DEV_ID_82546GB_SERDES 0x107B
		#define E1000_DEV_ID_82546GB_PCIE 0x108A
		#define E1000_DEV_ID_82547EI 0x1019
		#define E1000_DEV_ID_82571EB_COPPER 0x105E
		#define E1000_DEV_ID_82571EB_FIBER 0x105F
		#define E1000_DEV_ID_82571EB_SERDES 0x1060
		#define E1000_DEV_ID_82572EI_COPPER 0x107D
		#define E1000_DEV_ID_82572EI_FIBER 0x107E
		#define E1000_DEV_ID_82572EI_SERDES 0x107F
		#define E1000_DEV_ID_82573E 0x108B
		#define E1000_DEV_ID_82573E_IAMT 0x108C
		#define E1000_DEV_ID_82573L 0x109A

		#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099

		#define NODE_ADDRESS_SIZE 6
		#define ETH_LENGTH_OF_ADDRESS 6
		@@ -833,6 +841,8 @@ struct e1000_ffvt_entry {
		#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
		#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX

		#define E1000_DISABLE_SERDES_LOOPBACK 0x0400

		/* Register Set. (82543, 82544)
		*
		* Registers are defined to be 32 bits and should be accessed as 32 bit values.
		@@ -853,6 +863,7 @@ struct e1000_ffvt_entry {
		#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
		#define E1000_FLA 0x0001C /* Flash Access - RW */
		#define E1000_MDIC 0x00020 /* MDI Control - RW */
		#define E1000_SCTL 0x00024 /* SerDes Control - RW */
		#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
		#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
		#define E1000_FCT 0x00030 /* Flow Control Type - RW */
		@@ -864,6 +875,12 @@ struct e1000_ffvt_entry {
		#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
		#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
		#define E1000_RCTL 0x00100 /* RX Control - RW */
		#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
		#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
		#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
		#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
		#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
		#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
		#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
		#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
		#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
		@@ -895,6 +912,12 @@ struct e1000_ffvt_entry {
		#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
		#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
		#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
		#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
		#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
		#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
		#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
		#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
		#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
		#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
		#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
		#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
		@@ -980,15 +1003,15 @@ struct e1000_ffvt_entry {
		#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
		#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
		#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
		#define E1000_IAC 0x4100 /* Interrupt Assertion Count */
		#define E1000_ICRXPTC 0x4104 /* Interrupt Cause Rx Packet Timer Expire Count */
		#define E1000_ICRXATC 0x4108 /* Interrupt Cause Rx Absolute Timer Expire Count */
		#define E1000_ICTXPTC 0x410C /* Interrupt Cause Tx Packet Timer Expire Count */
		#define E1000_ICTXATC 0x4110 /* Interrupt Cause Tx Absolute Timer Expire Count */
		#define E1000_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */
		#define E1000_ICTXQMTC 0x411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
		#define E1000_ICRXDMTC 0x4120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
		#define E1000_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */
		#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
		#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
		#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
		#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
		#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
		#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
		#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
		#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
		#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
		#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
		#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
		#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
		@@ -1018,6 +1041,14 @@ struct e1000_ffvt_entry {
		#define E1000_FWSM 0x05B54 /* FW Semaphore */
		#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
		#define E1000_HICR 0x08F00 /* Host Inteface Control */

		/* RSS registers */
		#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
		#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
		#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
		#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
		#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
		#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
		/* Register Set (82542)
		*
		* Some of the 82542 registers are located at different offsets than they are
		@@ -1032,6 +1063,7 @@ struct e1000_ffvt_entry {
		#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
		#define E1000_82542_FLA E1000_FLA
		#define E1000_82542_MDIC E1000_MDIC
		#define E1000_82542_SCTL E1000_SCTL
		#define E1000_82542_FCAL E1000_FCAL
		#define E1000_82542_FCAH E1000_FCAH
		#define E1000_82542_FCT E1000_FCT
		@@ -1049,6 +1081,18 @@ struct e1000_ffvt_entry {
		#define E1000_82542_RDLEN 0x00118
		#define E1000_82542_RDH 0x00120
		#define E1000_82542_RDT 0x00128
		#define E1000_82542_RDTR0 E1000_82542_RDTR
		#define E1000_82542_RDBAL0 E1000_82542_RDBAL
		#define E1000_82542_RDBAH0 E1000_82542_RDBAH
		#define E1000_82542_RDLEN0 E1000_82542_RDLEN
		#define E1000_82542_RDH0 E1000_82542_RDH
		#define E1000_82542_RDT0 E1000_82542_RDT
		#define E1000_82542_RDTR1 0x00130
		#define E1000_82542_RDBAL1 0x00138
		#define E1000_82542_RDBAH1 0x0013C
		#define E1000_82542_RDLEN1 0x00140
		#define E1000_82542_RDH1 0x00148
		#define E1000_82542_RDT1 0x00150
		#define E1000_82542_FCRTH 0x00160
		#define E1000_82542_FCRTL 0x00168
		#define E1000_82542_FCTTV E1000_FCTTV
		@@ -1197,6 +1241,13 @@ struct e1000_ffvt_entry {
		#define E1000_82542_ICRXOC E1000_ICRXOC
		#define E1000_82542_HICR E1000_HICR

		#define E1000_82542_CPUVEC E1000_CPUVEC
		#define E1000_82542_MRQC E1000_MRQC
		#define E1000_82542_RETA E1000_RETA
		#define E1000_82542_RSSRK E1000_RSSRK
		#define E1000_82542_RSSIM E1000_RSSIM
		#define E1000_82542_RSSIR E1000_RSSIR

		/* Statistics counters collected by the MAC */
		struct e1000_hw_stats {
		uint64_t crcerrs;
		@@ -1336,6 +1387,7 @@ struct e1000_hw {
		boolean_t serdes_link_down;
		boolean_t tbi_compatibility_en;
		boolean_t tbi_compatibility_on;
		boolean_t laa_is_present;
		boolean_t phy_reset_disable;
		boolean_t fc_send_xon;
		boolean_t fc_strict_ieee;
		@@ -1374,6 +1426,7 @@ struct e1000_hw {
		#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
		#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
		#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
		#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
		#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
		#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
		#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
		@@ -1491,6 +1544,8 @@ struct e1000_hw {
		#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
		#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
		#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
		#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
		#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
		#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
		#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */

		@@ -1524,6 +1579,7 @@ struct e1000_hw {
		#define E1000_LEDCTL_LED2_BLINK 0x00800000
		#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
		#define E1000_LEDCTL_LED3_MODE_SHIFT 24
		#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
		#define E1000_LEDCTL_LED3_IVRT 0x40000000
		#define E1000_LEDCTL_LED3_BLINK 0x80000000

		@@ -1784,6 +1840,16 @@ struct e1000_hw {
		#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
		#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */

		/* Multiple Receive Queue Control */
		#define E1000_MRQC_ENABLE_MASK 0x00000003
		#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
		#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
		#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
		#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
		#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
		#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000
		#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
		#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000

		/* Definitions for power management and wakeup registers */
		/* Wake Up Control */
		@@ -1928,6 +1994,7 @@ struct e1000_host_command_info {
		#define E1000_MDALIGN 4096

		#define E1000_GCR_BEM32 0x00400000
		#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
		/* Function Active and Power State to MNG */
		#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
		#define E1000_FACTPS_LAN0_VALID 0x00000004
		@@ -1980,6 +2047,7 @@ struct e1000_host_command_info {
		/* EEPROM Word Offsets */
		#define EEPROM_COMPAT 0x0003
		#define EEPROM_ID_LED_SETTINGS 0x0004
		#define EEPROM_VERSION 0x0005
		#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
		#define EEPROM_PHY_CLASS_WORD 0x0007
		#define EEPROM_INIT_CONTROL1_REG 0x000A
		@@ -1990,6 +2058,8 @@ struct e1000_host_command_info {
		#define EEPROM_FLASH_VERSION 0x0032
		#define EEPROM_CHECKSUM_REG 0x003F

		#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */

		/* Word definitions for ID LED Settings */
		#define ID_LED_RESERVED_0000 0x0000
		#define ID_LED_RESERVED_FFFF 0xFFFF
		@@ -2108,6 +2178,8 @@ struct e1000_host_command_info {
		#define E1000_PBA_22K 0x0016
		#define E1000_PBA_24K 0x0018
		#define E1000_PBA_30K 0x001E
		#define E1000_PBA_32K 0x0020
		#define E1000_PBA_38K 0x0026
		#define E1000_PBA_40K 0x0028
		#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */

		@@ -2592,11 +2664,11 @@ struct e1000_host_command_info {

		/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
		#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
		#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 128
		#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113

		/* The precision error of the cable length is +/- 10 meters */
		#define IGP01E1000_AGC_RANGE 10
		#define IGP02E1000_AGC_RANGE 10
		#define IGP02E1000_AGC_RANGE 15

		/* IGP01E1000 PCS Initialization register */
		/* bits 3:6 in the PCS registers stores the channels polarity */

drivers/net/e1000/e1000_main.c

+94 −8

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