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Commit 867920f8 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo: implement nvif event source 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 6c6ae061

drivers/gpu/drm/nouveau/core/engine/fifo/base.c

+44 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <core/event.h>

#include <nvif/unpack.h>

#include <nvif/class.h>

#include <nvif/event.h>



#include <engine/dmaobj.h>

#include <engine/fifo.h>
@@ -168,6 +169,49 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) 
	iowrite32_native(data, chan->user + addr);

}



int

nouveau_fifo_uevent_ctor(void *data, u32 size, struct nvkm_notify *notify)

{

	union {

		struct nvif_notify_uevent_req none;

	} *req = data;

	int ret;



	if (nvif_unvers(req->none)) {

		notify->size  = sizeof(struct nvif_notify_uevent_rep);

		notify->types = 1;

		notify->index = 0;

	}



	return ret;

}



void

nouveau_fifo_uevent(struct nouveau_fifo *fifo)

{

	struct nvif_notify_uevent_rep rep = {

	};

	nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep));

}



int

_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type,

			   struct nvkm_event **event)

{

	struct nouveau_fifo *fifo = (void *)object->engine;

	switch (type) {

	case G82_CHANNEL_DMA_V0_NTFY_UEVENT:

		if (nv_mclass(object) >= G82_CHANNEL_DMA) {

			*event = &fifo->uevent;

			return 0;

		}

		break;

	default:

		break;

	}

	return -EINVAL;

}



static int

nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)

{

drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c

+2 −1
Original line number Diff line number Diff line
@@ -255,6 +255,7 @@ nv04_fifo_ofuncs = { 
	.map  = _nouveau_fifo_channel_map,

	.rd32 = _nouveau_fifo_channel_rd32,

	.wr32 = _nouveau_fifo_channel_wr32,

	.ntfy = _nouveau_fifo_channel_ntfy

};



static struct nouveau_oclass
@@ -550,7 +551,7 @@ nv04_fifo_intr(struct nouveau_subdev *subdev) 
			}



			if (status & 0x40000000) {

				nvkm_event_send(&priv->base.uevent, 1, 0, NULL, 0);

				nouveau_fifo_uevent(&priv->base);

				nv_wr32(priv, 0x002100, 0x40000000);

				status &= ~0x40000000;

			}

drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c

+1 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ nv10_fifo_ofuncs = { 
	.map  = _nouveau_fifo_channel_map,

	.rd32 = _nouveau_fifo_channel_rd32,

	.wr32 = _nouveau_fifo_channel_wr32,

	.ntfy = _nouveau_fifo_channel_ntfy

};



static struct nouveau_oclass

drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c

+1 −0
Original line number Diff line number Diff line
@@ -120,6 +120,7 @@ nv17_fifo_ofuncs = { 
	.map  = _nouveau_fifo_channel_map,

	.rd32 = _nouveau_fifo_channel_rd32,

	.wr32 = _nouveau_fifo_channel_wr32,

	.ntfy = _nouveau_fifo_channel_ntfy

};



static struct nouveau_oclass

drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c

+1 −0
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ nv40_fifo_ofuncs = { 
	.map  = _nouveau_fifo_channel_map,

	.rd32 = _nouveau_fifo_channel_rd32,

	.wr32 = _nouveau_fifo_channel_wr32,

	.ntfy = _nouveau_fifo_channel_ntfy

};



static struct nouveau_oclass