Unverified Commit 85fb3526 authored Feb 11, 2019 by Maxime Ripard

drm/sun4i: dsi: Restrict DSI tcon clock divider

The current code allows the TCON clock divider to have a range between 4
and 127 when feeding the DSI controller.

The only display supported so far had a display clock rate that ended up
using a divider of 4, but testing with other displays show that only 4
seems to be functional.

This also aligns with what Allwinner is doing in their BSP, so let's just
hardcode that we want a divider of 4 when using the DSI output.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/074e88ae472f5e0492e26939c74b44fb4125ffbd.1549896081.git-series.maxime.ripard@bootlin.com

parent fd347df1

drivers/gpu/drm/sun4i/sun4i_tcon.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
		u32 block_space, start_delay;
		u32 tcon_div;

		tcon->dclk_min_div = 4;
		tcon->dclk_max_div = 127;
		tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
		tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;

		sun4i_tcon0_mode_set_common(tcon, mode);

+2 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,8 @@
		#include <drm/drm_encoder.h>
		#include <drm/drm_mipi_dsi.h>

		#define SUN6I_DSI_TCON_DIV 4

		struct sun6i_dsi {
		struct drm_connector connector;
		struct drm_encoder encoder;