Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 85947127 authored by Raghu Ananya Arabolu's avatar Raghu Ananya Arabolu Committed by Gerrit - the friendly Code Review server
Browse files

msm: kgsl: Do not program CP_LPAC_ROQ_THRESHOLDS registers 



CP ucode (v0.76 onwards) handles the programming of these registers.

Change-Id: I233458160ea1f7ef55db49d751b9a50f84820a68
Signed-off-by: default avatarRaghu Ananya Arabolu <rarabolu@codeaurora.org>
parent e1bdeb41

drivers/gpu/msm/a6xx_reg.h

+0 −2
Original line number Diff line number Diff line
@@ -119,8 +119,6 @@ 
#define A6XX_VSC_ADDR_MODE_CNTL          0xC01



/* LPAC registers */

#define A6XX_CP_LPAC_ROQ_THRESHOLDS_1    0xB32

#define A6XX_CP_LPAC_ROQ_THRESHOLDS_2    0xB33

#define A6XX_CP_LPAC_PROG_FIFO_SIZE      0xB34



/* RBBM registers */

drivers/gpu/msm/adreno_a6xx.c

+1 −6
Original line number Diff line number Diff line
@@ -473,13 +473,8 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

	}



	if (adreno_is_a660(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_2,

						0x00800060);

		kgsl_regwrite(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_1,

						0x40202016);

	if (adreno_is_a660(adreno_dev))

		kgsl_regwrite(device, A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);

	}



	if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

		/* For A612 and A610 Mem pool size is reduced to 48 */