Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8577c319 authored by Mika Kuoppala's avatar Mika Kuoppala
Browse files

drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update 



Register DBUF_CTL_S2 is read and it's value is not used. As
there is no explanation why we should prime the hardware with
read, remove it as spurious.

Fixes: aa9664ff ("drm/i915/icl: Enable 2nd DBuf slice only when needed")
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181109140924.2663-1-mika.kuoppala@linux.intel.com
parent 704e504b

drivers/gpu/drm/i915/intel_runtime_pm.c

+1 −3
Original line number Diff line number Diff line
@@ -3236,8 +3236,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) 
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,

			    u8 req_slices)

{

	u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;

	u32 val;

	const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;

	bool ret;



	if (req_slices > intel_dbuf_max_slices(dev_priv)) {
@@ -3248,7 +3247,6 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, 
	if (req_slices == hw_enabled_slices || req_slices == 0)

		return;



	val = I915_READ(DBUF_CTL_S2);

	if (req_slices > hw_enabled_slices)

		ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);

	else