Merge bfc9c0c05cf08822f425f28ce1400203482a79cf on remote branch (85122493) · Commits · e / devices / android_kernel_fairphone_FP5

fw/htt.h

+239 −2

Original line number	Diff line number	Diff line
		@@ -223,9 +223,12 @@
		* 3.98 Add htt_tx_tcl_metadata_v2 def.
		* 3.99 Add HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ, _UNMAP_REQ, _MAP_REPORT_REQ and
		* HTT_T2H_SAWF_DEF_QUEUES_MAP_REPORT_CONF defs.
		* 3.100 Add htt_tx_wbm_completion_v3 def.
		* 3.101 Add HTT_UL_OFDMA_USER_INFO_V1_BITMAP defs.
		* 3.102 Add HTT_H2T_MSG_TYPE_MSI_SETUP def.
		*/
		#define HTT_CURRENT_VERSION_MAJOR 3
		#define HTT_CURRENT_VERSION_MINOR 99
		#define HTT_CURRENT_VERSION_MINOR 102

		#define HTT_NUM_TX_FRAG_DESC 1024

		@@ -717,6 +720,8 @@ typedef enum {
		HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, /* htt_tx_selfgen_be_sched_status_stats_tlv */
		HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */
		HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */
		HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */
		HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv */


		HTT_STATS_MAX_TAG,
		@@ -781,6 +786,7 @@ enum htt_h2t_msg_type {
		HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c,
		HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d,
		HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e,
		HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f,

		/* keep this last */
		HTT_H2T_NUM_MSGS
		@@ -2659,6 +2665,7 @@ typedef enum {
		HTT_TX_FW2WBM_REINJECT_REASON_ARP,
		HTT_TX_FW2WBM_REINJECT_REASON_DHCP,
		HTT_TX_FW2WBM_REINJECT_REASON_FLOW_CONTROL,
		HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST,

		HTT_TX_FW2WBM_REINJECT_REASON_MAX,
		} htt_tx_fw2wbm_reinject_reason_t;
		@@ -2833,6 +2840,88 @@ PREPACK struct htt_tx_wbm_completion_v2 {
		((_var) \|= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \
		} while (0)

		/**
		* @brief HTT TX WBM Completion from firmware to host (V3)
		* @details
		* This structure applies only to WLAN chips that contain WLAN Buffer Mgmt
		* (WBM) offload HW.
		* This structure is passed from firmware to host overlayed on wbm_release_ring
		* For software based completions, release_source_module will
		* be set to WIFIRELEASE_SOURCE_FW_E. Host SW is expected to inspect using
		* struct wbm_release_ring and then switch to this after looking at
		* release_source_module.
		* Due to overlap with WBM block, htt_tx_wbm_completion_v3 will be used
		* by new generations of targets.
		*/
		PREPACK struct htt_tx_wbm_completion_v3 {
		A_UINT32
		used_by_hw0; /* Refer to struct wbm_release_ring */
		A_UINT32
		used_by_hw1; /* Refer to struct wbm_release_ring */
		A_UINT32
		used_by_hw2: 13, /* Refer to struct wbm_release_ring */
		tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
		used_by_hw3: 15;
		A_UINT32
		reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
		exception_frame: 1,
		rsvd0: 27; /* For future use */
		A_UINT32
		data0: 32; /* data0,1 and 2 changes based on tx_status type
		* if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
		* or HTT_TX_FW2WBM_TX_STATUS_TTL, struct htt_tx_wbm_transmit_status will be used.
		* if HTT_TX_FW2WBM_TX_STATUS_REINJECT, struct htt_tx_wbm_reinject_status will be used.
		* if HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY, struct htt_tx_wbm_mec_addr_notify will be used.
		*/
		A_UINT32
		data1: 32;
		A_UINT32
		data2: 32;
		A_UINT32
		rsvd1: 20,
		used_by_hw4: 12; /* Refer to struct wbm_release_ring */
		} POSTPACK;


		#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000
		#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13
		#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F
		#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0
		#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010
		#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4


		#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \
		(((_var) & HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M) >> \
		HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)

		#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TX_STATUS, _val); \
		((_var) \|= ((_val) << HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S)); \
		} while (0)

		#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_GET(_var) \
		(((_var) & HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M) >> \
		HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)

		#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON, _val); \
		((_var) \|= ((_val) << HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S)); \
		} while (0)

		#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_GET(_var) \
		(((_var) & HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M) >> \
		HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)

		#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_EXP_FRAME, _val); \
		((_var) \|= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \
		} while (0)


		typedef enum {
		TX_FRAME_TYPE_UNDEFINED = 0,
		TX_FRAME_TYPE_EAPOL = 1,
		@@ -4765,6 +4854,112 @@ PREPACK struct htt_wdi_ipa_op_request_t
		((_var) \|= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \
		} while (0)

		/*
		* @brief host -> target HTT_MSI_SETUP message
		*
		* MSG_TYPE => HTT_H2T_MSG_TYPE_MSI_SETUP
		*
		* @details
		* After target is booted up, host can send MSI setup message so that
		* target sets up HW registers based on setup message.
		*
		* The message would appear as follows:
		* \|31 24\|23 16\|15\|14 8\|7 0\|
		* \|---------------+-----------------+-----------------+-----------------\|
		* \| reserved \| msi_type \| pdev_id \| msg_type \|
		* \|---------------------------------------------------------------------\|
		* \| msi_addr_lo \|
		* \|---------------------------------------------------------------------\|
		* \| msi_addr_hi \|
		* \|---------------------------------------------------------------------\|
		* \| msi_data \|
		* \|---------------------------------------------------------------------\|
		*
		* The message is interpreted as follows:
		* dword0 - b'0:7 - msg_type: This will be set to
		* 0x1f (HTT_H2T_MSG_TYPE_MSI_SETUP)
		* b'8:15 - pdev_id:
		* 0 (for rings at SOC/UMAC level),
		* 1/2/3 mac id (for rings at LMAC level)
		* b'16:23 - msi_type: identify which msi registers need to be setup
		* more details can be got from enum htt_msi_setup_type
		* b'24:31 - reserved
		* dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
		* dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
		* dword10 - b'0:31 - ring_msi_data: MSI data configured by host
		*/
		PREPACK struct htt_msi_setup_t {
		A_UINT32 msg_type: 8,
		pdev_id: 8,
		msi_type: 8,
		reserved: 8;
		A_UINT32 msi_addr_lo;
		A_UINT32 msi_addr_hi;
		A_UINT32 msi_data;
		} POSTPACK;

		enum htt_msi_setup_type {
		HTT_PPDU_END_MSI_SETUP_TYPE,

		/* Insert new types here*/
		};

		#define HTT_MSI_SETUP_SZ (sizeof(struct htt_msi_setup_t))
		#define HTT_MSI_SETUP_PDEV_ID_M 0x0000ff00
		#define HTT_MSI_SETUP_PDEV_ID_S 8
		#define HTT_MSI_SETUP_PDEV_ID_GET(_var) \
		(((_var) & HTT_MSI_SETUP_PDEV_ID_M) >> \
		HTT_MSI_SETUP_PDEV_ID_S)
		#define HTT_MSI_SETUP_PDEV_ID_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_MSI_SETUP_PDEV_ID, _val); \
		((_var) \|= ((_val) << HTT_MSI_SETUP_PDEV_ID_S)); \
		} while (0)

		#define HTT_MSI_SETUP_MSI_TYPE_M 0x00ff0000
		#define HTT_MSI_SETUP_MSI_TYPE_S 16
		#define HTT_MSI_SETUP_MSI_TYPE_GET(_var) \
		(((_var) & HTT_MSI_SETUP_MSI_TYPE_M) >> \
		HTT_MSI_SETUP_MSI_TYPE_S)
		#define HTT_MSI_SETUP_MSI_TYPE_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_TYPE, _val); \
		((_var) \|= ((_val) << HTT_MSI_SETUP_MSI_TYPE_S)); \
		} while (0)

		#define HTT_MSI_SETUP_MSI_ADDR_LO_M 0xffffffff
		#define HTT_MSI_SETUP_MSI_ADDR_LO_S 0
		#define HTT_MSI_SETUP_MSI_ADDR_LO_GET(_var) \
		(((_var) & HTT_MSI_SETUP_MSI_ADDR_LO_M) >> \
		HTT_MSI_SETUP_MSI_ADDR_LO_S)
		#define HTT_MSI_SETUP_MSI_ADDR_LO_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_LO, _val); \
		((_var) \|= ((_val) << HTT_MSI_SETUP_MSI_ADDR_LO_S)); \
		} while (0)

		#define HTT_MSI_SETUP_MSI_ADDR_HI_M 0xffffffff
		#define HTT_MSI_SETUP_MSI_ADDR_HI_S 0
		#define HTT_MSI_SETUP_MSI_ADDR_HI_GET(_var) \
		(((_var) & HTT_MSI_SETUP_MSI_ADDR_HI_M) >> \
		HTT_MSI_SETUP_MSI_ADDR_HI_S)
		#define HTT_MSI_SETUP_MSI_ADDR_HI_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_ADDR_HI, _val); \
		((_var) \|= ((_val) << HTT_MSI_SETUP_MSI_ADDR_HI_S)); \
		} while (0)

		#define HTT_MSI_SETUP_MSI_DATA_M 0xffffffff
		#define HTT_MSI_SETUP_MSI_DATA_S 0
		#define HTT_MSI_SETUP_MSI_DATA_GET(_var) \
		(((_var) & HTT_MSI_SETUP_MSI_DATA_M) >> \
		HTT_MSI_SETUP_MSI_DATA_S)
		#define HTT_MSI_SETUP_MSI_DATA_SET(_var, _val) \
		do { \
		HTT_CHECK_SET_VAL(HTT_MSI_SETUP_MSI_DATA, _val); \
		((_var) \|= ((_val) << HTT_MSI_SETUP_MSI_DATA_S)); \
		} while (0)

		/*
		* @brief host -> target HTT_SRING_SETUP message
		*
		@@ -16343,7 +16538,28 @@ struct htt_ul_ofdma_user_info_v0_bitmap_w1 {
		HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W1
		};

		/* htt_up_ofdma_user_info_v0_bitmap shows what bitfields are within the info */

		#define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \
		A_UINT32 w0_fw_rsvd:27; \
		A_UINT32 w0_sub_version:3; /* set to a value of “0” on WKK/Beryllium targets (future expansion) */ \
		A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \
		A_UINT32 w0_version:1; /* set to a value of “1” to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */

		struct htt_ul_ofdma_user_info_v1_bitmap_w0 {
		HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0
		};

		#define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1 \
		A_UINT32 w1_unused_0_to_18:19; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */ \
		A_UINT32 w1_trig_type:4; \
		A_UINT32 w1_unused_23_to_31:9; /* Guaranteed to be set to 0, can be used for future expansion without bumping version again. */

		struct htt_ul_ofdma_user_info_v1_bitmap_w1 {
		HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1
		};


		/* htt_ul_ofdma_user_info_v0_bitmap shows what bitfields are within the info */
		PREPACK struct htt_ul_ofdma_user_info_v0_bitmap {
		union {
		A_UINT32 word0;
		@@ -16359,6 +16575,27 @@ PREPACK struct htt_ul_ofdma_user_info_v0_bitmap {
		};
		} POSTPACK;

		/*
		* htt_ul_ofdma_user_info_v1_bitmap bits are aligned to
		* htt_ul_ofdma_user_info_v0_bitmap, based on the w0_version
		* this should be picked.
		*/
		PREPACK struct htt_ul_ofdma_user_info_v1_bitmap {
		union {
		A_UINT32 word0;
		struct {
		HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0
		};
		};
		union {
		A_UINT32 word1;
		struct {
		HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W1
		};
		};
		} POSTPACK;


		enum HTT_UL_OFDMA_TRIG_TYPE {
		HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0,
		HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP,

fw/htt_stats.h

+121 −0

Original line number	Diff line number	Diff line
		@@ -506,6 +506,25 @@ typedef enum {
		HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA,
		} htt_tx_rate_stats_upload_t;

		/* htt_rx_ul_trigger_stats_upload_t
		* Enumerations for specifying which stats to upload in response to
		* HTT_DBG_EXT_STATS_PDEV_TX_RATE.
		*/
		typedef enum {
		/* Upload 11ax UL OFDMA RX Trigger stats
		*
		* TLV: htt_rx_pdev_ul_trigger_stats_tlv
		*/
		HTT_RX_UL_TRIGGER_STATS_UPLOAD_11AX_OFDMA,

		/*
		* Upload 11be UL OFDMA RX Trigger stats
		*
		* TLV: htt_rx_pdev_be_ul_trigger_stats_tlv
		*/
		HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA,
		} htt_rx_ul_trigger_stats_upload_t;

		#define HTT_STATS_MAX_STRING_SZ32 4
		#define HTT_STATS_MACID_INVALID 0xff
		#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10
		@@ -3181,6 +3200,26 @@ typedef struct {
		A_UINT32 vdev_id_mismatch_cnt;
		} htt_tx_de_cmn_stats_tlv;

		#define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0) & 0xffff)
		#define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff)

		/* Rx debug info for status rings */
		typedef struct {
		htt_tlv_hdr_t tlv_hdr;
		/* BIT [15 : 0] :- max possible number of entries in respective ring (size of the ring in terms of entries)
		* BIT [16 : 31] :- current number of entries occupied in respective ring
		*/
		A_UINT32 entry_status_sw2rxdma;
		A_UINT32 entry_status_rxdma2reo;
		A_UINT32 entry_status_reo2sw1;
		A_UINT32 entry_status_reo2sw4;
		A_UINT32 entry_status_refillringipa;
		A_UINT32 entry_status_refillringhost;
		/* datarate - Moving Average of Number of Entries */
		A_UINT32 datarate_refillringipa;
		A_UINT32 datarate_refillringhost;
		} htt_rx_fw_ring_stats_tlv_v;

		/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_DE_INFO
		* TLV_TAGS:
		* - HTT_STATS_TX_DE_CMN_TAG
		@@ -3953,6 +3992,26 @@ typedef struct {
		*/
		#define HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS 7 /* includes 996x2 */

		typedef enum {
		HTT_RX_PDEV_STATS_BE_RU_SIZE_26,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_52,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_52_26,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_106,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_106_26,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_242,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_484,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_484_242,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484_242,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2_484,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3_484,
		HTT_RX_PDEV_STATS_BE_RU_SIZE_996x4,
		HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS,
		} HTT_RX_PDEV_STATS_BE_RU_SIZE;

		#define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff
		#define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0

		@@ -4220,6 +4279,68 @@ typedef struct {
		htt_rx_pdev_ul_trigger_stats_tlv ul_trigger_tlv;
		} htt_rx_pdev_ul_trigger_stats_t;

		typedef struct {
		htt_tlv_hdr_t tlv_hdr;

		/* BIT [ 7 : 0] :- mac_id
		* BIT [31 : 8] :- reserved
		*/
		A_UINT32 mac_id__word;

		A_UINT32 rx_11be_ul_ofdma;

		A_UINT32 be_ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS];
		A_UINT32 be_ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS];
		A_UINT32 be_ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
		A_UINT32 be_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS];
		A_UINT32 be_ul_ofdma_rx_stbc;
		A_UINT32 be_ul_ofdma_rx_ldpc;

		/*
		* These are arrays to hold the number of PPDUs that we received per RU.
		* E.g. PPDUs (data or non data) received in RU26 will be incremented in
		* array offset 0 and similarly RU52 will be incremented in array offset 1
		*/
		A_UINT32 be_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /* ppdu level */
		A_UINT32 be_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /* ppdu level */

		/*
		* These arrays hold Target RSSI (rx power the AP wants),
		* FD RSSI (rx power the AP sees) & Power headroom values of STAs
		* which can be identified by AIDs, during trigger based RX.
		* Array acts a circular buffer and holds values for last 5 STAs
		* in the same order as RX.
		*/
		/* uplink_sta_aid:
		* STA AID array for identifying which STA the
		* Target-RSSI / FD-RSSI / pwr headroom stats are for
		*/
		A_UINT32 be_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
		/* uplink_sta_target_rssi:
		* Trig Target RSSI for STA AID in same index - UNIT(dBm)
		*/
		A_INT32 be_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
		/* uplink_sta_fd_rssi:
		* Trig FD RSSI from STA AID in same index - UNIT(dBm)
		*/
		A_INT32 be_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
		/* uplink_sta_power_headroom:
		* Trig power headroom for STA AID in same idx - UNIT(dB)
		*/
		A_UINT32 be_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK];
		} htt_rx_pdev_be_ul_trigger_stats_tlv;

		/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
		* TLV_TAGS:
		* - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG
		* NOTE:
		* This structure is for documentation, and cannot be safely used directly.
		* Instead, use the constituent TLV structures to fill/parse.
		*/
		typedef struct {
		htt_rx_pdev_be_ul_trigger_stats_tlv ul_trigger_tlv;
		} htt_rx_pdev_be_ul_trigger_stats_t;

		typedef struct {
		htt_tlv_hdr_t tlv_hdr;

fw/wlan_defs.h

+12 −9

Original line number	Diff line number	Diff line
		@@ -1280,14 +1280,17 @@ struct wlan_dbg_tidq_stats {

		typedef enum {
		WLAN_DBG_DATA_STALL_NONE = 0,
		WLAN_DBG_DATA_STALL_VDEV_PAUSE, /* 1 */
		WLAN_DBG_DATA_STALL_HWSCHED_CMD_FILTER, /* 2 */
		WLAN_DBG_DATA_STALL_HWSCHED_CMD_FLUSH, /* 3 */
		WLAN_DBG_DATA_STALL_RX_REFILL_FAILED, /* 4 */
		WLAN_DBG_DATA_STALL_RX_FCS_LEN_ERROR, /* 5 */
		WLAN_DBG_DATA_STALL_MAC_WDOG_ERRORS, /* 6 / / Mac watch dog */
		WLAN_DBG_DATA_STALL_PHY_BB_WDOG_ERROR, /* 7 / / PHY watch dog */
		WLAN_DBG_DATA_STALL_POST_TIM_NO_TXRX_ERROR, /* 8 */
		WLAN_DBG_DATA_STALL_VDEV_PAUSE = 1,
		WLAN_DBG_DATA_STALL_HWSCHED_CMD_FILTER = 2,
		WLAN_DBG_DATA_STALL_HWSCHED_CMD_FLUSH = 3,
		WLAN_DBG_DATA_STALL_RX_REFILL_FAILED = 4,
		WLAN_DBG_DATA_STALL_RX_FCS_LEN_ERROR = 5,
		WLAN_DBG_DATA_STALL_MAC_WDOG_ERRORS = 6, /* Mac watch dog */
		WLAN_DBG_DATA_STALL_PHY_BB_WDOG_ERROR = 7, /* PHY watch dog */
		WLAN_DBG_DATA_STALL_POST_TIM_NO_TXRX_ERROR = 8,
		WLAN_DBG_DATA_STALL_CONSECUTIVE_NON_FLUSH = 9,
		WLAN_DBG_DATA_STALL_CONSECUTIVE_NOACK = 10,
		WLAN_DBG_DATA_STALL_CONSECUTIVE_LT_EXPIRY = 11,
		WLAN_DBG_DATA_STALL_MAX,
		} wlan_dbg_data_stall_type_e;

fw/wmi.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -145,6 +145,8 @@ typedef enum {
		GROUP_USAGE = 0x01,
		TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
		PMK_USAGE = 0x04, /* PMK cache */
		PASN_USAGE = 0x08, /* is PASN based key */
		LTF_USAGE = 0x10, /* is LTF key seed */
		} KEY_USAGE;
		/*
		* List of Events (target to host)

fw/wmi_services.h

+5 −1

Original line number	Diff line number	Diff line
		@@ -561,7 +561,11 @@ typedef enum {
		WMI_SERVICE_RTSCTS_FOR_UNICAST_MGMT_SUPPORT = 309, /* Indicates FW support RTSCTS for unicast management */
		WMI_SERVICE_DYNAMIC_VDEV_MAC_ADDR_UPDATE_SUPPORT = 310, /* FW supports dynamic vdev mac address updating */
		WMI_SERVICE_SAWF_LEVEL0 = 311, /* FW supports WMI_SAWF_SVC_CLASS CFG_CMD + DISABLE_CMD msgs */

		WMI_SERVICE_RTT_11AZ_NTB_SUPPORT = 312, /* FW support for 11AZ non trigger based ranging */
		WMI_SERVICE_RTT_11AZ_TB_SUPPORT = 313, /* FW support for 11AZ trigger based ranging */
		WMI_SERVICE_RTT_11AZ_MAC_SEC_SUPPORT = 314, /* FW support for 11AZ secure FTM */
		WMI_SERVICE_RTT_11AZ_MAC_PHY_SEC_SUPPORT = 315, /* FW support for 11AZ secure LTF + FTM */
		WMI_SERVICE_SPECTRAL_SESSION_INFO_SUPPORT = 316, /* Information corresponding to each Spectral scan session will be sent by the FW before the reports corresponding to that session are sent */

		WMI_MAX_EXT2_SERVICE