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Commit 84d6d0bf authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "interconnect: qcom: add virt_clk provider and QUP nodes"

parents 37c922d8 c4448eb8

drivers/interconnect/qcom/lahaina.c

+33 −3
Original line number Diff line number Diff line
@@ -55,6 +55,12 @@ DEFINE_QNODE(xm_sdc2, MASTER_SDCC_2, 1, 8, 1, 
		SLAVE_A2NOC_SNOC);

DEFINE_QNODE(xm_ufs_card, MASTER_UFS_CARD, 1, 8, 1,

		SLAVE_A2NOC_SNOC);

DEFINE_QNODE(qup0_core_master, MASTER_QUP_CORE_0, 1, 4, 1,

		SLAVE_QUP_CORE_0);

DEFINE_QNODE(qup1_core_master, MASTER_QUP_CORE_1, 1, 4, 1,

		SLAVE_QUP_CORE_1);

DEFINE_QNODE(qup2_core_master, MASTER_QUP_CORE_2, 1, 4, 1,

		SLAVE_QUP_CORE_2);

DEFINE_QNODE(qnm_gemnoc_cnoc, MASTER_GEM_NOC_CNOC, 1, 16, 56,

		SLAVE_AHB2PHY_SOUTH, SLAVE_AHB2PHY_NORTH,

		SLAVE_AOSS, SLAVE_APPSS,
@@ -192,6 +198,9 @@ DEFINE_QNODE(qns_a2noc_snoc, SLAVE_A2NOC_SNOC, 1, 16, 1, 
DEFINE_QNODE(qns_pcie_mem_noc, SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, 1,

		MASTER_ANOC_PCIE_GEM_NOC);

DEFINE_QNODE(srvc_aggre2_noc, SLAVE_SERVICE_A2NOC, 1, 4, 0);

DEFINE_QNODE(qup0_core_slave, SLAVE_QUP_CORE_0, 1, 4, 0);

DEFINE_QNODE(qup1_core_slave, SLAVE_QUP_CORE_1, 1, 4, 0);

DEFINE_QNODE(qup2_core_slave, SLAVE_QUP_CORE_2, 1, 4, 0);

DEFINE_QNODE(qhs_ahb2phy0, SLAVE_AHB2PHY_SOUTH, 1, 4, 0);

DEFINE_QNODE(qhs_ahb2phy1, SLAVE_AHB2PHY_NORTH, 1, 4, 0);

DEFINE_QNODE(qhs_aoss, SLAVE_AOSS, 1, 4, 0);
@@ -367,7 +376,6 @@ DEFINE_QBCM(bcm_sn14, "SN14", 1, false, 
		&qns_pcie_mem_noc);



static struct qcom_icc_bcm *aggre1_noc_bcms[] = {

	&bcm_qup1,

};



static struct qcom_icc_node *aggre1_noc_nodes[] = {
@@ -390,9 +398,7 @@ static struct qcom_icc_desc lahaina_aggre1_noc = { 
};



static struct qcom_icc_bcm *aggre2_noc_bcms[] = {

	&bcm_qup0,

	&bcm_ce0,

	&bcm_qup2,

	&bcm_sn5,

	&bcm_sn6,

	&bcm_sn14,
@@ -422,6 +428,28 @@ static struct qcom_icc_desc lahaina_aggre2_noc = { 
	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),

};



static struct qcom_icc_bcm *clk_virt_bcms[] = {

	&bcm_qup0,

	&bcm_qup1,

	&bcm_qup2,

};



static struct qcom_icc_node *clk_virt_nodes[] = {

	[MASTER_QUP_CORE_0] = &qup0_core_master,

	[MASTER_QUP_CORE_1] = &qup1_core_master,

	[MASTER_QUP_CORE_2] = &qup2_core_master,

	[SLAVE_QUP_CORE_0] = &qup0_core_slave,

	[SLAVE_QUP_CORE_1] = &qup1_core_slave,

	[SLAVE_QUP_CORE_2] = &qup2_core_slave,

};



static struct qcom_icc_desc lahaina_clk_virt = {

	.nodes = clk_virt_nodes,

	.num_nodes = ARRAY_SIZE(clk_virt_nodes),

	.bcms = clk_virt_bcms,

	.num_bcms = ARRAY_SIZE(clk_virt_bcms),

};



static struct qcom_icc_bcm *config_noc_bcms[] = {

	&bcm_cn0,

	&bcm_cn1,
@@ -777,6 +805,8 @@ static const struct of_device_id qnoc_of_match[] = { 
	  .data = &lahaina_aggre1_noc},

	{ .compatible = "qcom,lahaina-aggre2_noc",

	  .data = &lahaina_aggre2_noc},

	{ .compatible = "qcom,lahaina-clk_virt",

	  .data = &lahaina_clk_virt},

	{ .compatible = "qcom,lahaina-config_noc",

	  .data = &lahaina_config_noc},

	{ .compatible = "qcom,lahaina-dc_noc",

include/dt-bindings/interconnect/qcom,lahaina.h

+42 −36
Original line number Diff line number Diff line
@@ -40,24 +40,27 @@ 
#define MASTER_VIDEO_P0				31

#define MASTER_VIDEO_P1				32

#define MASTER_VIDEO_PROC				33

#define MASTER_CRYPTO				34

#define MASTER_IPA				35

#define MASTER_MDP0				36

#define MASTER_MDP1				37

#define MASTER_CDSP_PROC				38

#define MASTER_PIMEM				39

#define MASTER_ROTATOR				40

#define MASTER_GIC				41

#define MASTER_PCIE_0				42

#define MASTER_PCIE_1				43

#define MASTER_QDSS_DAP				44

#define MASTER_QDSS_ETR				45

#define MASTER_SDCC_2				46

#define MASTER_SDCC_4				47

#define MASTER_UFS_CARD				48

#define MASTER_UFS_MEM				49

#define MASTER_USB3_0				50

#define MASTER_USB3_1				51

#define MASTER_QUP_CORE_0				34

#define MASTER_QUP_CORE_1				35

#define MASTER_QUP_CORE_2				36

#define MASTER_CRYPTO				37

#define MASTER_IPA				38

#define MASTER_MDP0				39

#define MASTER_MDP1				40

#define MASTER_CDSP_PROC				41

#define MASTER_PIMEM				42

#define MASTER_ROTATOR				43

#define MASTER_GIC				44

#define MASTER_PCIE_0				45

#define MASTER_PCIE_1				46

#define MASTER_QDSS_DAP				47

#define MASTER_QDSS_ETR				48

#define MASTER_SDCC_2				49

#define MASTER_SDCC_4				50

#define MASTER_UFS_CARD				51

#define MASTER_UFS_MEM				52

#define MASTER_USB3_0				53

#define MASTER_USB3_1				54

#define SLAVE_EBI1				512

#define SLAVE_AHB2PHY_SOUTH				513

#define SLAVE_AHB2PHY_NORTH				514
@@ -128,23 +131,26 @@ 
#define SLAVE_MEM_NOC_PCIE_SNOC				579

#define SLAVE_ANOC_PCIE_GEM_NOC				580

#define SLAVE_SNOC_CFG				581

#define SLAVE_BOOT_IMEM				582

#define SLAVE_IMEM				583

#define SLAVE_PIMEM				584

#define SLAVE_SERVICE_NSP_NOC				585

#define SLAVE_SERVICE_A1NOC				586

#define SLAVE_SERVICE_A2NOC				587

#define SLAVE_SERVICE_CNOC				588

#define SLAVE_SERVICE_GEM_NOC_1				589

#define SLAVE_SERVICE_MNOC				590

#define SLAVE_SERVICES_LPASS_AML_NOC				591

#define SLAVE_SERVICE_LPASS_AG_NOC				592

#define SLAVE_SERVICE_GEM_NOC_2				593

#define SLAVE_SERVICE_SNOC				594

#define SLAVE_SERVICE_GEM_NOC				595

#define SLAVE_PCIE_0				596

#define SLAVE_PCIE_1				597

#define SLAVE_QDSS_STM				598

#define SLAVE_TCU				599

#define SLAVE_QUP_CORE_0				582

#define SLAVE_QUP_CORE_1				583

#define SLAVE_QUP_CORE_2				584

#define SLAVE_BOOT_IMEM				585

#define SLAVE_IMEM				586

#define SLAVE_PIMEM				587

#define SLAVE_SERVICE_NSP_NOC				588

#define SLAVE_SERVICE_A1NOC				589

#define SLAVE_SERVICE_A2NOC				590

#define SLAVE_SERVICE_CNOC				591

#define SLAVE_SERVICE_GEM_NOC_1				592

#define SLAVE_SERVICE_MNOC				593

#define SLAVE_SERVICES_LPASS_AML_NOC				594

#define SLAVE_SERVICE_LPASS_AG_NOC				595

#define SLAVE_SERVICE_GEM_NOC_2				596

#define SLAVE_SERVICE_SNOC				597

#define SLAVE_SERVICE_GEM_NOC				598

#define SLAVE_PCIE_0				599

#define SLAVE_PCIE_1				600

#define SLAVE_QDSS_STM				601

#define SLAVE_TCU				602



#endif