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Commit 84a9c4d5 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

arm64: dts: uniphier: add SD controller nodes 



Add SD controller nodes for LD20 and PXs3.
LD20 does not support the UHS mode, while PXs3 supports it.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent b0a6261f

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -572,6 +572,20 @@ 
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;

		};



		sd: sdhc@5a400000 {

			compatible = "socionext,uniphier-sd-v3.1.1";

			status = "disabled";

			reg = <0x5a400000 0x800>;

			interrupts = <0 76 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_sd>;

			clocks = <&sd_clk 0>;

			reset-names = "host";

			resets = <&sd_rst 0>;

			bus-width = <4>;

			cap-sd-highspeed;

		};



		soc_glue: soc-glue@5f800000 {

			compatible = "socionext,uniphier-ld20-soc-glue",

				     "simple-mfd", "syscon";

arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts

+4 −0
Original line number Diff line number Diff line
@@ -75,6 +75,10 @@ 
	status = "okay";

};



&sd {

	status = "okay";

};



&eth0 {

	status = "okay";

	phy-handle = <&ethphy0>;

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -363,6 +363,24 @@ 
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;

		};



		sd: sdhc@5a400000 {

			compatible = "socionext,uniphier-sd-v3.1.1";

			status = "disabled";

			reg = <0x5a400000 0x800>;

			interrupts = <0 76 4>;

			pinctrl-names = "default", "uhs";

			pinctrl-0 = <&pinctrl_sd>;

			pinctrl-1 = <&pinctrl_sd_uhs>;

			clocks = <&sd_clk 0>;

			reset-names = "host";

			resets = <&sd_rst 0>;

			bus-width = <4>;

			cap-sd-highspeed;

			sd-uhs-sdr12;

			sd-uhs-sdr25;

			sd-uhs-sdr50;

		};



		soc_glue: soc-glue@5f800000 {

			compatible = "socionext,uniphier-pxs3-soc-glue",

				     "simple-mfd", "syscon";