Commit 847b9dfc authored Aug 07, 2006 by Chris Dearman Committed by Ralf Baechle Sep 27, 2006

[MIPS] MT: Initialise all writable bits in Cause register to zero.



Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent bca70d24

arch/mips/kernel/smp-mt.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -203,7 +203,7 @@ void plat_smp_setup(void)
		write_vpe_c0_config( read_c0_config());

		/* make sure there are no software interrupts pending */
		write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1\|C_SW0));
		write_vpe_c0_cause(0);

		/* Propagate Config7 */
		write_vpe_c0_config7(read_c0_config7());