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Commit 846f5c62 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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[BNX2]: Fix default WoL setting. 



Change the default WoL setting to match the NVRAM's setting.  It
always defaulted to WoL disabled before and caused a lot of confusion
for users.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 489310a4

drivers/net/bnx2.c

+14 −6
Original line number Diff line number Diff line
@@ -6569,8 +6569,11 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 
		if (i != 2)

			bp->fw_version[j++] = '.';

	}

	if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &

	    BNX2_PORT_FEATURE_ASF_ENABLED) {

	reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);

	if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)

		bp->wol = 1;



	if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {

		bp->flags |= ASF_ENABLE_FLAG;



		for (i = 0; i < 30; i++) {
@@ -6640,11 +6643,14 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 
	bp->phy_port = PORT_TP;

	if (bp->phy_flags & PHY_SERDES_FLAG) {

		bp->phy_port = PORT_FIBRE;

		reg = REG_RD_IND(bp, bp->shmem_base +

				     BNX2_SHARED_HW_CFG_CONFIG);

		if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {

			bp->flags |= NO_WOL_FLAG;

			bp->wol = 0;

		}

		if (CHIP_NUM(bp) != CHIP_NUM_5706) {

			bp->phy_addr = 2;

			reg = REG_RD_IND(bp, bp->shmem_base +

					 BNX2_SHARED_HW_CFG_CONFIG);

			if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)

				bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;

		}
@@ -6659,8 +6665,10 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 


	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||

	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||

	    (CHIP_ID(bp) == CHIP_ID_5708_B1))

	    (CHIP_ID(bp) == CHIP_ID_5708_B1)) {

		bp->flags |= NO_WOL_FLAG;

		bp->wol = 0;

	}



	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {

		bp->tx_quick_cons_trip_int =

drivers/net/bnx2.h

+1 −0
Original line number Diff line number Diff line
@@ -6908,6 +6908,7 @@ struct fw_info { 
#define BNX2_SHARED_HW_CFG_LED_MODE_MAC		 0

#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1	 0x100

#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2	 0x200

#define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX	 0x8000



#define BNX2_SHARED_HW_CFG_CONFIG2		0x00000040

#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK	 0x00fff000