Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 84504930 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_for_4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull EDAC updates from Borislav Petkov:

 - Stratix10 SDRAM support to altera_edac (Thor Thayer)

 - the usual misc fixes all over the place

[ Also, shared branch for socfpga_stratix10.dtsi file changes with the
  socfpga tree ]

* tag 'edac_for_4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  EDAC, ghes: Make platform-based whitelisting x86-only
  EDAC, altera: Fix ARM64 build warning
  EDAC, skx: Fix skx_edac build error when ACPI_NFIT=m
  EDAC, ghes: Use BIT() macro
  EDAC, ghes: Add DDR4 and NVDIMM memory types
  EDAC, altera: Handle SDRAM Uncorrectable Errors on Stratix10
  Documentation: dt: edac: Move Altera SOCFPGA EDAC file
  EDAC, altera: Add support for Stratix10 SDRAM EDAC
  Documentation: dt: socfpga: Add Stratix10 ECC Manager binding
  EDAC, ghes: Remove unused argument to ghes_edac_report_mem_error()
  arm64: dts: stratix10: add sdram ecc
  EDAC, i7core: Fix spelling mistake: "redundacy" -> "redundancy"
  EDAC, ghes: Add a null pointer check in ghes_edac_unregister()
  ghes, EDAC: Fix ghes_edac registration
  arm64: dts: stratix10: Change pad skew values for EMAC0 PHY driver
  ARM: dts: consistently use 'atmel' as at24 manufacturer in cyclone5
  arm64: dts: stratix10: Add PL330 DMAC to Stratix10 dts
  arm64: dts: stratix10: enable i2c, add i2c periperals
  arm64: dts: stratix10: use clock bindings for the Stratix10 platform
parents 311da497 eaa3a1d4

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt→Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt

+35 −0
Original line number Original line Diff line number Diff line
@@ -231,3 +231,38 @@ Example: 
				     <48 IRQ_TYPE_LEVEL_HIGH>;

				     <48 IRQ_TYPE_LEVEL_HIGH>;

		};

		};

	};

	};



Stratix10 SoCFPGA ECC Manager

The Stratix10 SoC ECC Manager handles the IRQs for each peripheral

in a shared register similar to the Arria10. However, ECC requires

access to registers that can only be read from Secure Monitor with

SMC calls. Therefore the device tree is slightly different.



Required Properties:

- compatible : Should be "altr,socfpga-s10-ecc-manager"

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt.

- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller

- #interrupt-cells : must be set to 2.



Subcomponents:



SDRAM ECC

Required Properties:

- compatible : Should be "altr,sdram-edac-s10"

- interrupts : Should be single bit error interrupt, then double bit error

	interrupt, in this order.



Example:



	eccmgr {

		compatible = "altr,socfpga-s10-ecc-manager";

		interrupts = <0 15 4>, <0 95 4>;

		interrupt-controller;

		#interrupt-cells = <2>;



		sdramedac {

			compatible = "altr,sdram-edac-s10";

			interrupts = <16 4>, <48 4>;

		};

	};

arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts

+3 −3
Original line number Original line Diff line number Diff line
@@ -161,7 +161,7 @@ 
	};

	};





	at24@50 {

	at24@50 {

		compatible = "at24,24c01";

		compatible = "atmel,24c01";

		pagesize = <8>;

		pagesize = <8>;

		reg = <0x50>;

		reg = <0x50>;

	};

	};
@@ -213,7 +213,7 @@ 
			#size-cells = <0>;

			#size-cells = <0>;

			reg = <6>;

			reg = <6>;

			eeprom@51 {

			eeprom@51 {

				compatible = "at,24c01";

				compatible = "atmel,24c01";

				pagesize = <8>;

				pagesize = <8>;

				reg = <0x51>;

				reg = <0x51>;

			};

			};
@@ -224,7 +224,7 @@ 
			#size-cells = <0>;

			#size-cells = <0>;

			reg = <7>;

			reg = <7>;

			eeprom@51 {

			eeprom@51 {

				compatible = "at,24c01";

				compatible = "atmel,24c01";

				pagesize = <8>;

				pagesize = <8>;

				reg = <0x51>;

				reg = <0x51>;

			};

			};

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

+81 −2
Original line number Original line Diff line number Diff line
@@ -17,6 +17,7 @@ 
/dts-v1/;

/dts-v1/;

#include <dt-bindings/reset/altr,rst-mgr-s10.h>

#include <dt-bindings/reset/altr,rst-mgr-s10.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/stratix10-clock.h>





/ {

/ {

	compatible = "altr,socfpga-stratix10";

	compatible = "altr,socfpga-stratix10";
@@ -92,9 +93,32 @@ 
		interrupt-parent = <&intc>;

		interrupt-parent = <&intc>;

		ranges = <0 0 0 0xffffffff>;

		ranges = <0 0 0 0xffffffff>;





		clkmgr@ffd1000 {

		clkmgr: clock-controller@ffd10000 {

			compatible = "altr,clk-mgr";

			compatible = "intel,stratix10-clkmgr";

			reg = <0xffd10000 0x1000>;

			reg = <0xffd10000 0x1000>;

			#clock-cells = <1>;

		};



		clocks {

			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {

				#clock-cells = <0>;

				compatible = "fixed-clock";

			};



			cb_intosc_ls_clk: cb-intosc-ls-clk {

				#clock-cells = <0>;

				compatible = "fixed-clock";

			};



			f2s_free_clk: f2s-free-clk {

				#clock-cells = <0>;

				compatible = "fixed-clock";

			};



			osc1: osc1 {

				#clock-cells = <0>;

				compatible = "fixed-clock";

			};

		};

		};





		gmac0: ethernet@ff800000 {

		gmac0: ethernet@ff800000 {
@@ -105,6 +129,8 @@ 
			mac-address = [00 00 00 00 00 00];

			mac-address = [00 00 00 00 00 00];

			resets = <&rst EMAC0_RESET>;

			resets = <&rst EMAC0_RESET>;

			reset-names = "stmmaceth";

			reset-names = "stmmaceth";

			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;

			clock-names = "stmmaceth";

			status = "disabled";

			status = "disabled";

		};

		};
@@ -116,6 +142,8 @@ 
			mac-address = [00 00 00 00 00 00];

			mac-address = [00 00 00 00 00 00];

			resets = <&rst EMAC1_RESET>;

			resets = <&rst EMAC1_RESET>;

			reset-names = "stmmaceth";

			reset-names = "stmmaceth";

			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;

			clock-names = "stmmaceth";

			status = "disabled";

			status = "disabled";

		};

		};
@@ -127,6 +155,8 @@ 
			mac-address = [00 00 00 00 00 00];

			mac-address = [00 00 00 00 00 00];

			resets = <&rst EMAC2_RESET>;

			resets = <&rst EMAC2_RESET>;

			reset-names = "stmmaceth";

			reset-names = "stmmaceth";

			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;

			clock-names = "stmmaceth";

			status = "disabled";

			status = "disabled";

		};

		};
@@ -177,6 +207,7 @@ 
			reg = <0xffc02800 0x100>;

			reg = <0xffc02800 0x100>;

			interrupts = <0 103 4>;

			interrupts = <0 103 4>;

			resets = <&rst I2C0_RESET>;

			resets = <&rst I2C0_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -187,6 +218,7 @@ 
			reg = <0xffc02900 0x100>;

			reg = <0xffc02900 0x100>;

			interrupts = <0 104 4>;

			interrupts = <0 104 4>;

			resets = <&rst I2C1_RESET>;

			resets = <&rst I2C1_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -197,6 +229,7 @@ 
			reg = <0xffc02a00 0x100>;

			reg = <0xffc02a00 0x100>;

			interrupts = <0 105 4>;

			interrupts = <0 105 4>;

			resets = <&rst I2C2_RESET>;

			resets = <&rst I2C2_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -207,6 +240,7 @@ 
			reg = <0xffc02b00 0x100>;

			reg = <0xffc02b00 0x100>;

			interrupts = <0 106 4>;

			interrupts = <0 106 4>;

			resets = <&rst I2C3_RESET>;

			resets = <&rst I2C3_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -217,6 +251,7 @@ 
			reg = <0xffc02c00 0x100>;

			reg = <0xffc02c00 0x100>;

			interrupts = <0 107 4>;

			interrupts = <0 107 4>;

			resets = <&rst I2C4_RESET>;

			resets = <&rst I2C4_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -229,6 +264,9 @@ 
			fifo-depth = <0x400>;

			fifo-depth = <0x400>;

			resets = <&rst SDMMC_RESET>;

			resets = <&rst SDMMC_RESET>;

			reset-names = "reset";

			reset-names = "reset";

			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,

				 <&clkmgr STRATIX10_SDMMC_CLK>;

			clock-names = "biu", "ciu";

			status = "disabled";

			status = "disabled";

		};

		};
@@ -237,6 +275,25 @@ 
			reg = <0xffe00000 0x100000>;

			reg = <0xffe00000 0x100000>;

		};

		};





		pdma: pdma@ffda0000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0xffda0000 0x1000>;

			interrupts = <0 81 4>,

				     <0 82 4>,

				     <0 83 4>,

				     <0 84 4>,

				     <0 85 4>,

				     <0 86 4>,

				     <0 87 4>,

				     <0 88 4>,

				     <0 89 4>;

			#dma-cells = <1>;

			#dma-channels = <8>;

			#dma-requests = <32>;

			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;

			clock-names = "apb_pclk";

		};



		rst: rstmgr@ffd11000 {

		rst: rstmgr@ffd11000 {

			#reset-cells = <1>;

			#reset-cells = <1>;

			compatible = "altr,rst-mgr";

			compatible = "altr,rst-mgr";
@@ -288,24 +345,32 @@ 
			compatible = "snps,dw-apb-timer";

			compatible = "snps,dw-apb-timer";

			interrupts = <0 113 4>;

			interrupts = <0 113 4>;

			reg = <0xffc03000 0x100>;

			reg = <0xffc03000 0x100>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			clock-names = "timer";

		};

		};





		timer1: timer1@ffc03100 {

		timer1: timer1@ffc03100 {

			compatible = "snps,dw-apb-timer";

			compatible = "snps,dw-apb-timer";

			interrupts = <0 114 4>;

			interrupts = <0 114 4>;

			reg = <0xffc03100 0x100>;

			reg = <0xffc03100 0x100>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			clock-names = "timer";

		};

		};





		timer2: timer2@ffd00000 {

		timer2: timer2@ffd00000 {

			compatible = "snps,dw-apb-timer";

			compatible = "snps,dw-apb-timer";

			interrupts = <0 115 4>;

			interrupts = <0 115 4>;

			reg = <0xffd00000 0x100>;

			reg = <0xffd00000 0x100>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			clock-names = "timer";

		};

		};





		timer3: timer3@ffd00100 {

		timer3: timer3@ffd00100 {

			compatible = "snps,dw-apb-timer";

			compatible = "snps,dw-apb-timer";

			interrupts = <0 116 4>;

			interrupts = <0 116 4>;

			reg = <0xffd00100 0x100>;

			reg = <0xffd00100 0x100>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			clock-names = "timer";

		};

		};





		uart0: serial0@ffc02000 {

		uart0: serial0@ffc02000 {
@@ -315,6 +380,7 @@ 
			reg-shift = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			reg-io-width = <4>;

			resets = <&rst UART0_RESET>;

			resets = <&rst UART0_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -325,6 +391,7 @@ 
			reg-shift = <2>;

			reg-shift = <2>;

			reg-io-width = <4>;

			reg-io-width = <4>;

			resets = <&rst UART1_RESET>;

			resets = <&rst UART1_RESET>;

			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;

			status = "disabled";

			status = "disabled";

		};

		};
@@ -387,5 +454,17 @@ 
			resets = <&rst WATCHDOG3_RESET>;

			resets = <&rst WATCHDOG3_RESET>;

			status = "disabled";

			status = "disabled";

		};

		};



		eccmgr {

			compatible = "altr,socfpga-s10-ecc-manager";

			interrupts = <0 15 4>, <0 95 4>;

			interrupt-controller;

			#interrupt-cells = <2>;



			sdramedac {

				compatible = "altr,sdram-edac-s10";

				interrupts = <16 4>, <48 4>;

			};

		};

	};

	};

};
 
};

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts

+43 −1
Original line number Original line Diff line number Diff line
@@ -50,6 +50,21 @@ 
		/* We expect the bootloader to fill in the reg */

		/* We expect the bootloader to fill in the reg */

		reg = <0 0 0 0>;

		reg = <0 0 0 0>;

	};

	};



	ref_033v: 033-v-ref {

		compatible = "regulator-fixed";

		regulator-name = "0.33V";

		regulator-min-microvolt = <330000>;

		regulator-max-microvolt = <330000>;

	};



	soc {

		clocks {

			osc1 {

				clock-frequency = <25000000>;

			};

		};

	};

};

};





&gpio1 {

&gpio1 {
@@ -79,7 +94,7 @@ 
			rxd2-skew-ps = <420>; /* 0ps */

			rxd2-skew-ps = <420>; /* 0ps */

			rxd3-skew-ps = <420>; /* 0ps */

			rxd3-skew-ps = <420>; /* 0ps */

			txen-skew-ps = <0>; /* -420ps */

			txen-skew-ps = <0>; /* -420ps */

			txc-skew-ps = <1860>; /* 960ps */

			txc-skew-ps = <900>; /* 0ps */

			rxdv-skew-ps = <420>; /* 0ps */

			rxdv-skew-ps = <420>; /* 0ps */

			rxc-skew-ps = <1680>; /* 780ps */

			rxc-skew-ps = <1680>; /* 780ps */

		};

		};
@@ -105,3 +120,30 @@ 
&watchdog0 {

&watchdog0 {

	status = "okay";

	status = "okay";

};

};



&i2c1 {

	status = "okay";

	clock-frequency = <100000>;



	adc@14 {

		compatible = "lltc,ltc2497";

		reg = <0x14>;

		vref-supply = <&ref_033v>;

	};



	temp@4c {

		compatible = "maxim,max1619";

		reg = <0x4c>;

	};



	eeprom@51 {

		compatible = "atmel,24c32";

		reg = <0x51>;

		pagesize = <32>;

	};



	rtc@68 {

		compatible = "dallas,ds1339";

		reg = <0x68>;

	};

};

drivers/acpi/apei/ghes.c

+7 −9
Original line number Original line Diff line number Diff line
@@ -481,7 +481,7 @@ static void ghes_do_proc(struct ghes *ghes, 
		if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) {

		if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) {

			struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata);

			struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata);





			ghes_edac_report_mem_error(ghes, sev, mem_err);

			ghes_edac_report_mem_error(sev, mem_err);





			arch_apei_report_mem_error(sev, mem_err);

			arch_apei_report_mem_error(sev, mem_err);

			ghes_handle_memory_failure(gdata, sev);

			ghes_handle_memory_failure(gdata, sev);
@@ -1087,10 +1087,6 @@ static int ghes_probe(struct platform_device *ghes_dev) 
		goto err;

		goto err;

	}

	}





	rc = ghes_edac_register(ghes, &ghes_dev->dev);

	if (rc < 0)

		goto err;



	switch (generic->notify.type) {

	switch (generic->notify.type) {

	case ACPI_HEST_NOTIFY_POLLED:

	case ACPI_HEST_NOTIFY_POLLED:

		timer_setup(&ghes->timer, ghes_poll_func, TIMER_DEFERRABLE);

		timer_setup(&ghes->timer, ghes_poll_func, TIMER_DEFERRABLE);
@@ -1102,14 +1098,14 @@ static int ghes_probe(struct platform_device *ghes_dev) 
		if (rc) {

		if (rc) {

			pr_err(GHES_PFX "Failed to map GSI to IRQ for generic hardware error source: %d\n",

			pr_err(GHES_PFX "Failed to map GSI to IRQ for generic hardware error source: %d\n",

			       generic->header.source_id);

			       generic->header.source_id);

			goto err_edac_unreg;

			goto err;

		}

		}

		rc = request_irq(ghes->irq, ghes_irq_func, IRQF_SHARED,

		rc = request_irq(ghes->irq, ghes_irq_func, IRQF_SHARED,

				 "GHES IRQ", ghes);

				 "GHES IRQ", ghes);

		if (rc) {

		if (rc) {

			pr_err(GHES_PFX "Failed to register IRQ for generic hardware error source: %d\n",

			pr_err(GHES_PFX "Failed to register IRQ for generic hardware error source: %d\n",

			       generic->header.source_id);

			       generic->header.source_id);

			goto err_edac_unreg;

			goto err;

		}

		}

		break;

		break;
@@ -1132,14 +1128,16 @@ static int ghes_probe(struct platform_device *ghes_dev) 
	default:

	default:

		BUG();

		BUG();

	}

	}



	platform_set_drvdata(ghes_dev, ghes);

	platform_set_drvdata(ghes_dev, ghes);





	ghes_edac_register(ghes, &ghes_dev->dev);



	/* Handle any pending errors right away */

	/* Handle any pending errors right away */

	ghes_proc(ghes);

	ghes_proc(ghes);





	return 0;

	return 0;

err_edac_unreg:



	ghes_edac_unregister(ghes);

err:

err:

	if (ghes) {

	if (ghes) {

		ghes_fini(ghes);

		ghes_fini(ghes);