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Commit 8420eade authored by Jagadeesh Kona's avatar Jagadeesh Kona
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dt-bindings: clock: Update clock ID's of GPUCC and VideoCC for YUPIK 



Cleanup the clock ID's of GPU and Video clock controllers that are
not required to be controlled from HLOS.

Change-Id: I0d5b67ddbf3f080c70ed0a1a743f3bf7afef240f
Signed-off-by: default avatarJagadeesh Kona <jkona@codeaurora.org>
parent 33569a19

include/dt-bindings/clock/qcom,gpucc-yupik.h

+18 −31
Original line number Diff line number Diff line
@@ -9,37 +9,24 @@ 
/* GPU_CC clocks */

#define GPU_CC_PLL0						0

#define GPU_CC_PLL1						1

#define GPU_CC_ACD_AHB_CLK					2

#define GPU_CC_ACD_CXO_CLK					3

#define GPU_CC_AHB_CLK						4

#define GPU_CC_CB_CLK						5

#define GPU_CC_CRC_AHB_CLK					6

#define GPU_CC_CX_APB_CLK					7

#define GPU_CC_CX_GFX3D_CLK					8

#define GPU_CC_CX_GFX3D_SLV_CLK					9

#define GPU_CC_CX_GMU_CLK					10

#define GPU_CC_CX_SNOC_DVM_CLK					11

#define GPU_CC_CXO_AON_CLK					12

#define GPU_CC_CXO_CLK						13

#define GPU_CC_FREQ_MEASURE_CLK					14

#define GPU_CC_GMU_CLK_SRC					15

#define GPU_CC_GX_CXO_CLK					16

#define GPU_CC_GX_GFX3D_CLK					17

#define GPU_CC_GX_GFX3D_CLK_SRC					18

#define GPU_CC_GX_GMU_CLK					19

#define GPU_CC_GX_VSENSE_CLK					20

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				21

#define GPU_CC_HUB_AHB_DIV_CLK_SRC				22

#define GPU_CC_HUB_AON_CLK					23

#define GPU_CC_HUB_CLK_SRC					24

#define GPU_CC_HUB_CX_INT_CLK					25

#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC				26

#define GPU_CC_MND1X_0_GFX3D_CLK				27

#define GPU_CC_MND1X_1_GFX3D_CLK				28

#define GPU_CC_RBCPR_AHB_CLK					29

#define GPU_CC_RBCPR_CLK					30

#define GPU_CC_RBCPR_CLK_SRC					31

#define GPU_CC_SLEEP_CLK					32

#define GPU_CC_AHB_CLK						2

#define GPU_CC_CB_CLK						3

#define GPU_CC_CRC_AHB_CLK					4

#define GPU_CC_CX_GMU_CLK					5

#define GPU_CC_CX_SNOC_DVM_CLK					6

#define GPU_CC_CXO_AON_CLK					7

#define GPU_CC_CXO_CLK						8

#define GPU_CC_GMU_CLK_SRC					9

#define GPU_CC_GX_GMU_CLK					10

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				11

#define GPU_CC_HUB_AHB_DIV_CLK_SRC				12

#define GPU_CC_HUB_AON_CLK					13

#define GPU_CC_HUB_CLK_SRC					14

#define GPU_CC_HUB_CX_INT_CLK					15

#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC				16

#define GPU_CC_MND1X_0_GFX3D_CLK				17

#define GPU_CC_MND1X_1_GFX3D_CLK				18

#define GPU_CC_SLEEP_CLK					19



/* GPU_CC power domains */

#define GPU_CC_CX_GDSC						0

include/dt-bindings/clock/qcom,videocc-yupik.h

+11 −12
Original line number Diff line number Diff line
@@ -8,18 +8,17 @@ 


/* VIDEO_CC clocks */

#define VIDEO_PLL0						0

#define VIDEO_CC_APB_CLK					1

#define VIDEO_CC_IRIS_AHB_CLK					2

#define VIDEO_CC_IRIS_CLK_SRC					3

#define VIDEO_CC_MVS0_AXI_CLK					4

#define VIDEO_CC_MVS0_CORE_CLK					5

#define VIDEO_CC_MVSC_CORE_CLK					6

#define VIDEO_CC_MVSC_CTL_AXI_CLK				7

#define VIDEO_CC_SLEEP_CLK					8

#define VIDEO_CC_SLEEP_CLK_SRC					9

#define VIDEO_CC_VENUS_AHB_CLK					10

#define VIDEO_CC_XO_CLK						11

#define VIDEO_CC_XO_CLK_SRC					12

#define VIDEO_CC_IRIS_AHB_CLK					1

#define VIDEO_CC_IRIS_CLK_SRC					2

#define VIDEO_CC_MVS0_AXI_CLK					3

#define VIDEO_CC_MVS0_CORE_CLK					4

#define VIDEO_CC_MVSC_CORE_CLK					5

#define VIDEO_CC_MVSC_CTL_AXI_CLK				6

#define VIDEO_CC_SLEEP_CLK					7

#define VIDEO_CC_SLEEP_CLK_SRC					8

#define VIDEO_CC_VENUS_AHB_CLK					9

#define VIDEO_CC_XO_CLK						10

#define VIDEO_CC_XO_CLK_SRC					11



/* VIDEO_CC power domains */

#define VIDEO_CC_MVS0_GDSC					0