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Commit 841c696f authored by Sai Srujana Oruganti's avatar Sai Srujana Oruganti
Browse files

disp: msm: dsi: add API to handle PHY programming during 0p9 collapse 



Add HW recommended programming sequence when PHY
is allowed to turn off during idle state.

Change-Id: Icdd50d5ebc338842a6629ec08fc0ef35453e1052
Signed-off-by: default avatarSai Srujana Oruganti <quic_osaisruj@quicinc.com>
parent cf46f5d3

msm/dsi/dsi_catalog.c

+2 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/errno.h>
@@ -293,6 +294,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy) 
		dsi_phy_hw_v4_0_cache_phy_timings;

	phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk;

	phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing;

	phy->ops.phy_idle_off = dsi_phy_hw_v4_0_phy_idle_off;

}



/**

msm/dsi/dsi_catalog.h

+2 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DSI_CATALOG_H_
@@ -125,6 +126,7 @@ void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy); 
void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable);

void dsi_phy_hw_v4_0_commit_phy_timing(struct dsi_phy_hw *phy,

		struct dsi_phy_per_lane_cfgs *timing);

void dsi_phy_hw_v4_0_phy_idle_off(struct dsi_phy_hw *phy);



/* DSI controller common ops */

u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

msm/dsi/dsi_phy.c

+3 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/of_device.h>
@@ -356,6 +357,8 @@ static int dsi_phy_settings_init(struct platform_device *pdev, 


	phy->allow_phy_power_off = of_property_read_bool(pdev->dev.of_node,

			"qcom,panel-allow-phy-poweroff");

	phy->hw.clamp_enable = of_property_read_bool(pdev->dev.of_node,

			"qcom,phy-clamp-enable");



	of_property_read_u32(pdev->dev.of_node,

			"qcom,dsi-phy-regulator-min-datarate-bps",

msm/dsi/dsi_phy_hw.h

+3 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DSI_PHY_HW_H_
@@ -354,6 +355,7 @@ struct dsi_phy_hw_ops { 
 * @length:                Length of the DSI dynamic refresh register base map.

 * @index:                 Instance ID of the controller.

 * @version:               DSI PHY version.

 * @clamp_enable           True if phy clamp is enabled

 * @phy_clamp_base:        Base address of phy clamp register map.

 * @feature_map:           Features supported by DSI PHY.

 * @ops:                   Function pointer to PHY operations.
@@ -366,6 +368,7 @@ struct dsi_phy_hw { 
	u32 index;



	enum dsi_phy_version version;

	bool clamp_enable;

	void __iomem *phy_clamp_base;



	DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES);

msm/dsi/dsi_phy_hw_v4_0.c

+9 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/math64.h>
@@ -858,3 +859,11 @@ void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable) 
	DSI_W32(phy, DSIPHY_CMN_LANE_CTRL1, reg);

	wmb(); /* make sure request is set */

}



void dsi_phy_hw_v4_0_phy_idle_off(struct dsi_phy_hw *phy)

{

	if (phy->version >= DSI_PHY_VERSION_4_2 && phy->clamp_enable) {

		DSI_W32(phy, DSIPHY_CMN_CTRL_4, 0x1);

		DSI_W32(phy, DSIPHY_CMN_CTRL_3, 0x0);

	}

}