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Commit 840dd4c6 authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
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drm/amd/powerplay: set UVD clocks bypass mode for Polaris10 



Saves power when not in use.

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a8bd3e1c

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+2 −1
Original line number Diff line number Diff line
@@ -858,7 +858,8 @@ static int uvd_v6_0_set_clockgating_state(void *handle, 
	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;

	static int curstate = -1;



	if (adev->asic_type == CHIP_FIJI)

	if (adev->asic_type == CHIP_FIJI ||

			adev->asic_type == CHIP_POLARIS10)

		uvd_v6_set_bypass_mode(adev, enable);



	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c

+6 −0
Original line number Diff line number Diff line
@@ -106,11 +106,17 @@ int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 
	data->uvd_power_gated = bgate;



	if (bgate) {

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_CG_STATE_GATE);

		polaris10_update_uvd_dpm(hwmgr, true);

		polaris10_phm_powerdown_uvd(hwmgr);

	} else {

		polaris10_phm_powerup_uvd(hwmgr);

		polaris10_update_uvd_dpm(hwmgr, false);

		cgs_set_clockgating_state(hwmgr->device,

				AMD_IP_BLOCK_TYPE_UVD,

				AMD_PG_STATE_UNGATE);

	}



	return 0;