Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 83c58a55 authored by Nipun Gupta's avatar Nipun Gupta Committed by Shawn Guo
Browse files

arm64: dts: ls1088: add smmu device node 



This patch also adds the iommu-map property in fsl-mc node, so
that fsl-mc can use iommu.

Signed-off-by: default avatarNipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 881e90d2

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

+91 −1
Original line number Diff line number Diff line
@@ -518,6 +518,96 @@ 
			status = "disabled";

		};



		smmu: iommu@5000000 {

			compatible = "arm,mmu-500";

			reg = <0 0x5000000 0 0x800000>;

			#iommu-cells = <1>;

			stream-match-mask = <0x7C00>;

			#global-interrupts = <12>;

				     // global secure fault

			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				     // combined secure

				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				     // global non-secure fault

				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				     // combined non-secure

				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				     // performance counter interrupts 0-7

				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,

				     // per context interrupt, 64 interrupts

				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

		};



		cluster1_core0_watchdog: wdt@c000000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;
@@ -579,6 +669,7 @@ 
			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */

			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */

			msi-parent = <&its>;

			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */

			#address-cells = <3>;

			#size-cells = <1>;
@@ -652,5 +743,4 @@ 
			method = "smc";

		};

	};



};