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Commit 83be81e3 authored by Matthias Kaehlcke's avatar Matthias Kaehlcke Committed by Heiko Stuebner
Browse files

ARM: dts: rockchip: raise CPU trip point temperature for veyron to 100 degC 



This value matches what is used by the downstream Chrome OS 3.14
kernel, the 'official' kernel for veyron devices. Keep the temperature
for 'speedy' at 90°C, as in the downstream kernel.

Increase the temperature for a hardware shutdown to 125°C, which
matches the downstream configuration and gives the system a chance
to shut down orderly at the criticial trip point.

Signed-off-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1c047902

arch/arm/boot/dts/rk3288-veyron-speedy.dts

+4 −0
Original line number Original line Diff line number Diff line
@@ -64,6 +64,10 @@ 
	temperature = <70000>;

	temperature = <70000>;

};

};





&cpu_crit {

	temperature = <90000>;

};



&edp {

&edp {

	/delete-property/pinctrl-names;

	/delete-property/pinctrl-names;

	/delete-property/pinctrl-0;

	/delete-property/pinctrl-0;

arch/arm/boot/dts/rk3288-veyron.dtsi

+5 −0
Original line number Original line Diff line number Diff line
@@ -123,6 +123,10 @@ 
	cpu0-supply = <&vdd_cpu>;

	cpu0-supply = <&vdd_cpu>;

};

};





&cpu_crit {

	temperature = <100000>;

};



/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */

/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */

&cpu_opp_table {

&cpu_opp_table {

	/delete-node/ opp-312000000;

	/delete-node/ opp-312000000;
@@ -394,6 +398,7 @@ 




	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */

	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */

	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */

	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */

	rockchip,hw-tshut-temp = <125000>;

};

};





&uart0 {

&uart0 {