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Commit 8389b869 authored by Marc Gonzalez's avatar Marc Gonzalez Committed by Bjorn Andersson
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arm64: dts: qcom: msm8998: Add ANOC1 SMMU node 

The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB.
(*) Aggregate Network-on-Chip #1

Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18



Signed-off-by: default avatarMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 693e8244

arch/arm64/boot/dts/qcom/msm8998.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -859,6 +859,21 @@ 
			#thermal-sensor-cells = <1>;

		};



		anoc1_smmu: iommu@1680000 {

			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";

			reg = <0x01680000 0x10000>;

			#iommu-cells = <1>;



			#global-interrupts = <0>;

			interrupts =

				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;

		};



		tcsr_mutex_regs: syscon@1f40000 {

			compatible = "syscon";

			reg = <0x1f40000 0x20000>;