Merge tag 'clk-v4.7-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next (811a087c) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/samsung/clk-exynos3250.c

+15 −0

Original line number	Original line	Diff line number	Diff line
	@@ -302,10 +302,12 @@ static struct samsung_mux_clock mux_clks[] __initdata = {

	/* SRC_FSYS */		/* SRC_FSYS */
	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),		MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
			MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),		MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),		MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),

	/* SRC_PERIL0 */		/* SRC_PERIL0 */
			MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
	MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),		MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
	MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),		MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),

	@@ -389,7 +391,13 @@ static struct samsung_div_clock div_clks[] __initdata = {
	CLK_SET_RATE_PARENT, 0),		CLK_SET_RATE_PARENT, 0),
	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),		DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),

			/* DIV_FSYS2 */
			DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
			CLK_SET_RATE_PARENT, 0),
			DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),

	/* DIV_PERIL0 */		/* DIV_PERIL0 */
			DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),		DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
	DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),		DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),

	@@ -538,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
	GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",		GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
	GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
			GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
			GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",		GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
	GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",		GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
	@@ -552,6 +562,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
	GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),		GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",		GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
	GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),		GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),

			GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
			GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
	GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",		GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
	GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),		GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
	GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",		GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
	@@ -630,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),		GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),		GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),		GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
			GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),		GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),		GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),		GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
	@@ -649,6 +663,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
	GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),		GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
	GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),		GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
	GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),		GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
			GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
	GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),		GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
	GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),		GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
	};		};

drivers/clk/samsung/clk-exynos5420.c

+47 −30

Original line number	Original line	Diff line number	Diff line
	@@ -554,8 +554,8 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
	};		};

	static struct samsung_div_clock exynos5800_div_clks[] __initdata = {		static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
	DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),		DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
			"mout_aclk400_wcore", DIV_TOP0, 16, 3),
	DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",		DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
	DIV_TOP8, 16, 3),		DIV_TOP8, 16, 3),
	DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",		DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
	@@ -607,8 +607,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
	};		};

	static struct samsung_div_clock exynos5420_div_clks[] __initdata = {		static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
	DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",		DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
	DIV_TOP0, 16, 3),		"mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
	};		};

	static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {		static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
	@@ -785,31 +785,47 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),		DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
	DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),		DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),

	DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),		DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
	DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),		DIV_TOP0, 0, 3),
	DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),		DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
	DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),		DIV_TOP0, 4, 3),
	DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),		DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
	DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),		DIV_TOP0, 8, 3),
	DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),		DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
			DIV_TOP0, 12, 3),
	DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",		DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
	DIV_TOP1, 0, 3),		DIV_TOP0, 20, 3),
	DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",		DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
	DIV_TOP1, 4, 3),		DIV_TOP0, 24, 3),
	DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),		DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
	DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",		DIV_TOP0, 28, 3),
	DIV_TOP1, 16, 3),		DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
	DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),		"mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
	DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),		DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
	DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),		"mout_aclk333_432_isp", DIV_TOP1, 4, 3),
			DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
	DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),		DIV_TOP1, 8, 6),
	DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),		DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
	DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),		"mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
	DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),		DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
	DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),		DIV_TOP1, 20, 3),
	DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),		DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
			DIV_TOP1, 24, 3),
			DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
			DIV_TOP1, 28, 3),

			DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
			DIV_TOP2, 8, 3),
			DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
			DIV_TOP2, 12, 3),
			DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
			16, 3),
			DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
			DIV_TOP2, 20, 3),
			DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
			"mout_aclk300_disp1", DIV_TOP2, 24, 3),
			DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
			DIV_TOP2, 28, 3),

	/* DISP1 Block */		/* DISP1 Block */
	DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),		DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
	@@ -817,7 +833,8 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
	DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),		DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
	DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),		DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
	DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),		DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
	DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),		DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
			"mout_aclk400_disp1", DIV_TOP2, 4, 3),

	/* Audio Block */		/* Audio Block */
	DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),		DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),

include/dt-bindings/clock/exynos3250.h

+10 −1

Original line number	Original line	Diff line number	Diff line
	@@ -79,6 +79,8 @@
	#define CLK_MOUT_CORE 58		#define CLK_MOUT_CORE 58
	#define CLK_MOUT_APLL 59		#define CLK_MOUT_APLL 59
	#define CLK_MOUT_ACLK_266_SUB 60		#define CLK_MOUT_ACLK_266_SUB 60
			#define CLK_MOUT_UART2 61
			#define CLK_MOUT_MMC2 62

	/* Dividers */		/* Dividers */
	#define CLK_DIV_GPL 64		#define CLK_DIV_GPL 64
	@@ -127,6 +129,9 @@
	#define CLK_DIV_CORE 107		#define CLK_DIV_CORE 107
	#define CLK_DIV_HPM 108		#define CLK_DIV_HPM 108
	#define CLK_DIV_COPY 109		#define CLK_DIV_COPY 109
			#define CLK_DIV_UART2 110
			#define CLK_DIV_MMC2_PRE 111
			#define CLK_DIV_MMC2 112

	/* Gates */		/* Gates */
	#define CLK_ASYNC_G3D 128		#define CLK_ASYNC_G3D 128
	@@ -223,6 +228,8 @@
	#define CLK_BLOCK_MFC 219		#define CLK_BLOCK_MFC 219
	#define CLK_BLOCK_CAM 220		#define CLK_BLOCK_CAM 220
	#define CLK_SMIES 221		#define CLK_SMIES 221
			#define CLK_UART2 222
			#define CLK_SDMMC2 223

	/* Special clocks */		/* Special clocks */
	#define CLK_SCLK_JPEG 224		#define CLK_SCLK_JPEG 224
	@@ -249,12 +256,14 @@
	#define CLK_SCLK_SPI0 245		#define CLK_SCLK_SPI0 245
	#define CLK_SCLK_UART1 246		#define CLK_SCLK_UART1 246
	#define CLK_SCLK_UART0 247		#define CLK_SCLK_UART0 247
			#define CLK_SCLK_UART2 248
			#define CLK_SCLK_MMC2 249

	/*		/*
	* Total number of clocks of main CMU.		* Total number of clocks of main CMU.
	* NOTE: Must be equal to last clock ID increased by one.		* NOTE: Must be equal to last clock ID increased by one.
	*/		*/
	#define CLK_NR_CLKS 248		#define CLK_NR_CLKS 250

	/*		/*
	* CMU DMC		* CMU DMC

include/dt-bindings/clock/exynos5420.h

+23 −1

Original line number	Original line	Diff line number	Diff line
	@@ -217,8 +217,30 @@

	/* divider clocks */		/* divider clocks */
	#define CLK_DOUT_PIXEL 768		#define CLK_DOUT_PIXEL 768
			#define CLK_DOUT_ACLK400_WCORE 769
			#define CLK_DOUT_ACLK400_ISP 770
			#define CLK_DOUT_ACLK400_MSCL 771
			#define CLK_DOUT_ACLK200 772
			#define CLK_DOUT_ACLK200_FSYS2 773
			#define CLK_DOUT_ACLK100_NOC 774
			#define CLK_DOUT_PCLK200_FSYS 775
			#define CLK_DOUT_ACLK200_FSYS 776
			#define CLK_DOUT_ACLK333_432_GSCL 777
			#define CLK_DOUT_ACLK333_432_ISP 778
			#define CLK_DOUT_ACLK66 779
			#define CLK_DOUT_ACLK333_432_ISP0 780
			#define CLK_DOUT_ACLK266 781
			#define CLK_DOUT_ACLK166 782
			#define CLK_DOUT_ACLK333 783
			#define CLK_DOUT_ACLK333_G2D 784
			#define CLK_DOUT_ACLK266_G2D 785
			#define CLK_DOUT_ACLK_G3D 786
			#define CLK_DOUT_ACLK300_JPEG 787
			#define CLK_DOUT_ACLK300_DISP1 788
			#define CLK_DOUT_ACLK300_GSCL 789
			#define CLK_DOUT_ACLK400_DISP1 790

	/* must be greater than maximal clock id */		/* must be greater than maximal clock id */
	#define CLK_NR_CLKS 769		#define CLK_NR_CLKS 791

	#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */		#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */