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Commit 80f48a55 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gpucc-blair: Scale both cx and gx rails for gfx3d clock"

parents b05a0f59 1cdfc65d

drivers/clk/qcom/gpucc-blair.c

+17 −3
Original line number Diff line number Diff line
@@ -23,12 +23,10 @@ 


static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_gx, VDD_HIGH_L1 + 1, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_gx, VDD_NUM, 2, vdd_gx_corner);



static struct clk_vdd_class *gpu_cc_blair_regulators[] = {

	&vdd_cx,

	&vdd_mx,

	&vdd_gx,

};



enum {
@@ -468,6 +466,22 @@ static int gpu_cc_blair_probe(struct platform_device *pdev) 
	struct regmap *regmap;

	int ret;



	vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gx");

	if (IS_ERR(vdd_gx.regulator[0])) {

		if (!(PTR_ERR(vdd_gx.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");

		return PTR_ERR(vdd_gx.regulator[0]);

	}



	vdd_gx.regulator[1] = devm_regulator_get(&pdev->dev, "vdd_cx");

	if (IS_ERR(vdd_gx.regulator[1])) {

		if (!(PTR_ERR(vdd_gx.regulator[1]) == -EPROBE_DEFER))

			dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");

			return PTR_ERR(vdd_gx.regulator[1]);

	}



	vdd_cx.regulator[0] = vdd_gx.regulator[1];



	regmap = qcom_cc_map(pdev, &gpu_cc_blair_desc);

	if (IS_ERR(regmap))

		return PTR_ERR(regmap);

drivers/clk/qcom/vdd-level-holi.h

+13 −0
Original line number Diff line number Diff line
@@ -32,4 +32,17 @@ static int vdd_corner[] = { 
	[VDD_HIGH_L1]     = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,

};





static int vdd_gx_corner[] = {

	0, 0,

	RPM_SMD_REGULATOR_LEVEL_MIN_SVS, RPM_SMD_REGULATOR_LEVEL_MIN_SVS,

	RPM_SMD_REGULATOR_LEVEL_LOW_SVS, RPM_SMD_REGULATOR_LEVEL_LOW_SVS,

	RPM_SMD_REGULATOR_LEVEL_SVS, RPM_SMD_REGULATOR_LEVEL_SVS,

	RPM_SMD_REGULATOR_LEVEL_SVS_PLUS, RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,

	RPM_SMD_REGULATOR_LEVEL_NOM, RPM_SMD_REGULATOR_LEVEL_NOM,

	RPM_SMD_REGULATOR_LEVEL_NOM_PLUS, RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,

	RPM_SMD_REGULATOR_LEVEL_TURBO, RPM_SMD_REGULATOR_LEVEL_TURBO,

	RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR, RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,

};



#endif