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Commit 80bc94d1 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
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MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores 



Ingenic uses the CCA:1 bit to achieve write-combine memory writes.

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7401/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent fb020350

arch/mips/include/asm/pgtable-bits.h

+5 −0
Original line number Diff line number Diff line
@@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) 
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */

#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */



#elif defined(CONFIG_MACH_JZ4740)



/* Ingenic uses the WA bit to achieve write-combine memory writes */

#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)



#endif



#ifndef _CACHE_CACHABLE_NO_WA