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Commit 8051c0af authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Borislav Petkov
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EDAC, amd64: Add Fam17h scrubber support 



Fam17h has new register offsets and fields for setting up the DRAM
scrubber so add support for this.

Signed-off-by: default avatarYazen Ghannam <Yazen.Ghannam@amd.com>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1479423463-8536-17-git-send-email-Yazen.Ghannam@amd.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent a6c14dce

drivers/edac/amd64_edac.c

+38 −5
Original line number Original line Diff line number Diff line
@@ -164,8 +164,23 @@ static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, 
 * other archs, we might not have access to the caches directly.

 * other archs, we might not have access to the caches directly.

 */

 */





static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)

{

	/*

	 * Fam17h supports scrub values between 0x5 and 0x14. Also, the values

	 * are shifted down by 0x5, so scrubval 0x5 is written to the register

	 * as 0x0, scrubval 0x6 as 0x1, etc.

	 */

	if (scrubval >= 0x5 && scrubval <= 0x14) {

		scrubval -= 0x5;

		pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);

		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);

	} else {

		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);

	}

}

/*

/*

 * scan the scrub rate mapping table for a close or matching bandwidth value to

 * Scan the scrub rate mapping table for a close or matching bandwidth value to

 * issue. If requested is too big, then use last maximum value found.

 * issue. If requested is too big, then use last maximum value found.

 */

 */

static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)

static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
@@ -196,7 +211,9 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) 




	scrubval = scrubrates[i].scrubval;

	scrubval = scrubrates[i].scrubval;





	if (pvt->fam == 0x15 && pvt->model == 0x60) {

	if (pvt->fam == 0x17) {

		__f17h_set_scrubval(pvt, scrubval);

	} else if (pvt->fam == 0x15 && pvt->model == 0x60) {

		f15h_select_dct(pvt, 0);

		f15h_select_dct(pvt, 0);

		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);

		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);

		f15h_select_dct(pvt, 1);

		f15h_select_dct(pvt, 1);
@@ -233,18 +250,34 @@ static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw) 
static int get_scrub_rate(struct mem_ctl_info *mci)

static int get_scrub_rate(struct mem_ctl_info *mci)

{

{

	struct amd64_pvt *pvt = mci->pvt_info;

	struct amd64_pvt *pvt = mci->pvt_info;

	u32 scrubval = 0;

	int i, retval = -EINVAL;

	int i, retval = -EINVAL;

	u32 scrubval = 0;





	if (pvt->fam == 0x15) {

	switch (pvt->fam) {

	case 0x15:

		/* Erratum #505 */

		/* Erratum #505 */

		if (pvt->model < 0x10)

		if (pvt->model < 0x10)

			f15h_select_dct(pvt, 0);

			f15h_select_dct(pvt, 0);





		if (pvt->model == 0x60)

		if (pvt->model == 0x60)

			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);

			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);

	} else

		break;



	case 0x17:

		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);

		if (scrubval & BIT(0)) {

			amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);

			scrubval &= 0xF;

			scrubval += 0x5;

		} else {

			scrubval = 0;

		}

		break;



	default:

		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);

		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);

		break;

	}





	scrubval = scrubval & 0x001F;

	scrubval = scrubval & 0x001F;

drivers/edac/amd64_edac.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -204,6 +204,8 @@ 
#define DCT_SEL_HI			0x114

#define DCT_SEL_HI			0x114





#define F15H_M60H_SCRCTRL		0x1C8

#define F15H_M60H_SCRCTRL		0x1C8

#define F17H_SCR_BASE_ADDR		0x48

#define F17H_SCR_LIMIT_ADDR		0x4C





/*

/*

 * Function 3 - Misc Control

 * Function 3 - Misc Control