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Commit 80150b77 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Remove gmu_core_dev_enable_lm function 



This function writes to GMU CX/AO registers which can be
configured much earlier in gmu code itself instead.

Change-Id: I403ad8d2e0fa4f199663f0fb6234de3e59bd05f9
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent 317169ac

drivers/gpu/msm/adreno_a6xx.c

+0 −1
Original line number Diff line number Diff line
@@ -617,7 +617,6 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
	 * 3. HFI

	 * At this point, we are guaranteed all.

	 */

	gmu_core_dev_enable_lm(device);



	/* Configure LLCC */

	a6xx_llc_configure_gpu_scid(adreno_dev);

drivers/gpu/msm/adreno_a6xx_gmu.c

+36 −35
Original line number Diff line number Diff line
@@ -1117,6 +1117,40 @@ static void a6xx_gmu_mem_free(struct a6xx_gmu_device *gmu, 
	memset(md, 0, sizeof(*md));

}



static void a6xx_gmu_enable_lm(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	u32 val;



	memset(adreno_dev->busy_data.throttle_cycles, 0,

		sizeof(adreno_dev->busy_data.throttle_cycles));



	if (!adreno_dev->lm_enabled)

		return;



	/*

	 * For throttling, use the following counters for throttled cycles:

	 * XOCLK1: countable: 0x10

	 * XOCLK2: countable: 0x16 for newer hardware / 0x15 for others

	 * XOCLK3: countable: 0xf for newer hardware / 0x19 for others

	 *

	 * POWER_CONTROL_SELECT_0 controls counters 0 - 3, each selector

	 * is 8 bits wide.

	 */



	if (adreno_is_a620(adreno_dev) || adreno_is_a650(adreno_dev))

		val = (0x10 << 8) | (0x16 << 16) | (0x0f << 24);

	else

		val = (0x10 << 8) | (0x15 << 16) | (0x19 << 24);





	/* Make sure not to write over XOCLK0 */

	gmu_core_regrmw(device, A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0,

		0xffffff00, val);



	gmu_core_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 1);

}



/*

 * a6xx_gmu_fw_start() - set up GMU and start FW

 * @device: Pointer to KGSL device
@@ -1226,6 +1260,8 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device, 
	/* Populate the GMU version info before GMU boots */

	load_gmu_version_info(device);



	a6xx_gmu_enable_lm(device);



	/* Clear any previously set cm3 fault */

	atomic_set(&gmu->cm3_fault, 0);
@@ -1882,40 +1918,6 @@ static int a6xx_gmu_dcvs_set(struct kgsl_device *device, 
	return ret;

}



static void a6xx_gmu_enable_lm(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	u32 val;



	memset(adreno_dev->busy_data.throttle_cycles, 0,

		sizeof(adreno_dev->busy_data.throttle_cycles));



	if (!adreno_dev->lm_enabled)

		return;



	/*

	 * For throttling, use the following counters for throttled cycles:

	 * XOCLK1: countable: 0x10

	 * XOCLK2: countable: 0x16 for newer hardware / 0x15 for others

	 * XOCLK3: countable: 0xf for newer hardware / 0x19 for others

	 *

	 * POWER_CONTROL_SELECT_0 controls counters 0 - 3, each selector

	 * is 8 bits wide.

	 */



	if (adreno_is_a620(adreno_dev) || adreno_is_a650(adreno_dev))

		val = (0x10 << 8) | (0x16 << 16) | (0x0f << 24);

	else

		val = (0x10 << 8) | (0x15 << 16) | (0x19 << 24);





	/* Make sure not to write over XOCLK0 */

	gmu_core_regrmw(device, A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0,

		0xffffff00, val);



	gmu_core_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 1);

}



static int a6xx_gmu_ifpc_store(struct kgsl_device *device,

		unsigned int val)

{
@@ -2618,7 +2620,6 @@ static struct gmu_dev_ops a6xx_gmudev = { 
	.irq_enable = a6xx_gmu_irq_enable,

	.irq_disable = a6xx_gmu_irq_disable,

	.hfi_start_msg = a6xx_gmu_hfi_start_msg,

	.enable_lm = a6xx_gmu_enable_lm,

	.rpmh_gpu_pwrctrl = a6xx_gmu_rpmh_gpu_pwrctrl,

	.gx_is_on = a6xx_gmu_gx_is_on,

	.wait_for_lowest_idle = a6xx_gmu_wait_for_lowest_idle,

drivers/gpu/msm/kgsl_gmu_core.c

+0 −8
Original line number Diff line number Diff line
@@ -251,14 +251,6 @@ int gmu_core_dev_wait_for_lowest_idle(struct kgsl_device *device) 
	return 0;

}



void gmu_core_dev_enable_lm(struct kgsl_device *device)

{

	struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device);



	if (ops && ops->enable_lm)

		ops->enable_lm(device);

}



void gmu_core_dev_snapshot(struct kgsl_device *device,

		struct kgsl_snapshot *snapshot)

{

drivers/gpu/msm/kgsl_gmu_core.h

+0 −2
Original line number Diff line number Diff line
@@ -119,7 +119,6 @@ struct gmu_dev_ops { 
	void (*irq_enable)(struct kgsl_device *device);

	void (*irq_disable)(struct kgsl_device *device);

	int (*hfi_start_msg)(struct kgsl_device *device);

	void (*enable_lm)(struct kgsl_device *device);

	int (*rpmh_gpu_pwrctrl)(struct kgsl_device *device, unsigned int ops,

			unsigned int arg1, unsigned int arg2);

	int (*wait_for_lowest_idle)(struct kgsl_device *device);
@@ -207,7 +206,6 @@ int gmu_core_dev_oob_set(struct kgsl_device *device, enum oob_request req); 
void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req);

int gmu_core_dev_hfi_start_msg(struct kgsl_device *device);

int gmu_core_dev_wait_for_lowest_idle(struct kgsl_device *device);

void gmu_core_dev_enable_lm(struct kgsl_device *device);

void gmu_core_dev_snapshot(struct kgsl_device *device,

		struct kgsl_snapshot *snapshot);

bool gmu_core_dev_gx_is_on(struct kgsl_device *device);