Commit 7f6e7186 authored Aug 01, 2019 by Nikola Cornij Committed by Alex Deucher Aug 23, 2019

drm/amd/display: Zero-out dsc init regs



[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.

[how]
Zero-out PPS data structure at initialization time before it's
populated

Fixes: 1a9e3d45 ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end")
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 387ad34c

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
		{
		int i;

		memset(reg_vals, 0, sizeof(struct dsc_reg_values));

		/* Non-PPS values */
		reg_vals->dsc_clock_enable = 1;
		reg_vals->dsc_clock_gating_disable = 0;