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Commit 7f6233ca authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/ci: force pcie level before sclk and mclk 



Preferred ordering.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e745c3c9

drivers/gpu/drm/radeon/ci_dpm.c

+17 −17
Original line number Diff line number Diff line
@@ -4143,57 +4143,57 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev, 
	int ret;



	if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {

		if ((!pi->sclk_dpm_key_disabled) &&

		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

		if ((!pi->pcie_dpm_key_disabled) &&

		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

			levels = 0;

			tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;

			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;

			while (tmp >>= 1)

				levels++;

			if (levels) {

				ret = ci_dpm_force_state_sclk(rdev, levels);

				ret = ci_dpm_force_state_pcie(rdev, level);

				if (ret)

					return ret;

				for (i = 0; i < rdev->usec_timeout; i++) {

					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

					       CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;

					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &

					       CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;

					if (tmp == levels)

						break;

					udelay(1);

				}

			}

		}

		if ((!pi->mclk_dpm_key_disabled) &&

		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

		if ((!pi->sclk_dpm_key_disabled) &&

		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

			levels = 0;

			tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;

			tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;

			while (tmp >>= 1)

				levels++;

			if (levels) {

				ret = ci_dpm_force_state_mclk(rdev, levels);

				ret = ci_dpm_force_state_sclk(rdev, levels);

				if (ret)

					return ret;

				for (i = 0; i < rdev->usec_timeout; i++) {

					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

					       CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;

					       CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;

					if (tmp == levels)

						break;

					udelay(1);

				}

			}

		}

		if ((!pi->pcie_dpm_key_disabled) &&

		    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

		if ((!pi->mclk_dpm_key_disabled) &&

		    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

			levels = 0;

			tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;

			tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;

			while (tmp >>= 1)

				levels++;

			if (levels) {

				ret = ci_dpm_force_state_pcie(rdev, level);

				ret = ci_dpm_force_state_mclk(rdev, levels);

				if (ret)

					return ret;

				for (i = 0; i < rdev->usec_timeout; i++) {

					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &

					       CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;

					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

					       CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;

					if (tmp == levels)

						break;

					udelay(1);