Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7ed4e635 authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Add DCN2 HW Sequencer and Resource 



Add DCN2 resource definition and HW Sequencer changes.

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18eaea4b

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+15 −0
Original line number Diff line number Diff line
@@ -46,6 +46,9 @@ 
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

#include "dcn10/dcn10_resource.h"

#endif

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

#include "dcn20/dcn20_resource.h"

#endif

#include "dce120/dce120_resource.h"



#define DC_LOGGER_INIT(logger)
@@ -97,6 +100,12 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 
			dc_version = DCN_VERSION_1_01;

		break;

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	case FAMILY_NV:

		dc_version = DCN_VERSION_2_0;

		break;

#endif

	default:

		dc_version = DCE_VERSION_UNKNOWN;

		break;
@@ -151,6 +160,12 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, 
#endif





#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	case DCN_VERSION_2_0:

		res_pool = dcn20_create_resource_pool(init_data, dc);

		break;

#endif



	default:

		break;

	}

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

+88 −0
Original line number Diff line number Diff line
@@ -726,6 +726,56 @@ static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu) 


#endif //(CONFIG_DRM_AMD_DC_DCN1_0)



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)



static bool dcn20_lock_phy(struct dmcu *dmcu)

{

	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);



	/* If microcontroller is not running, do nothing */

	if (dmcu->dmcu_state != DMCU_RUNNING)

		return false;



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);



	/* setDMCUParam_Cmd */

	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);



	/* notifyDMCUMsg */

	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);



	return true;

}



static bool dcn20_unlock_phy(struct dmcu *dmcu)

{

	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);



	/* If microcontroller is not running, do nothing */

	if (dmcu->dmcu_state != DMCU_RUNNING)

		return false;



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);



	/* setDMCUParam_Cmd */

	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);



	/* notifyDMCUMsg */

	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);



	return true;

}



#endif //(CONFIG_DRM_AMD_DC_DCN2_0)



static const struct dmcu_funcs dce_funcs = {

	.dmcu_init = dce_dmcu_init,

	.load_iram = dce_dmcu_load_iram,
@@ -750,6 +800,21 @@ static const struct dmcu_funcs dcn10_funcs = { 
};

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

static const struct dmcu_funcs dcn20_funcs = {

	.dmcu_init = dcn10_dmcu_init,

	.load_iram = dcn10_dmcu_load_iram,

	.set_psr_enable = dcn10_dmcu_set_psr_enable,

	.setup_psr = dcn10_dmcu_setup_psr,

	.get_psr_state = dcn10_get_dmcu_psr_state,

	.set_psr_wait_loop = dcn10_psr_wait_loop,

	.get_psr_wait_loop = dcn10_get_psr_wait_loop,

	.is_dmcu_initialized = dcn10_is_dmcu_initialized,

	.lock_phy = dcn20_lock_phy,

	.unlock_phy = dcn20_unlock_phy

};

#endif



static void dce_dmcu_construct(

	struct dce_dmcu *dmcu_dce,

	struct dc_context *ctx,
@@ -812,6 +877,29 @@ struct dmcu *dcn10_dmcu_create( 
}

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

struct dmcu *dcn20_dmcu_create(

	struct dc_context *ctx,

	const struct dce_dmcu_registers *regs,

	const struct dce_dmcu_shift *dmcu_shift,

	const struct dce_dmcu_mask *dmcu_mask)

{

	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);



	if (dmcu_dce == NULL) {

		BREAK_TO_DEBUGGER();

		return NULL;

	}



	dce_dmcu_construct(

		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);



	dmcu_dce->base.funcs = &dcn20_funcs;



	return &dmcu_dce->base;

}

#endif



void dce_dmcu_destroy(struct dmcu **dmcu)

{

	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

+8 −0
Original line number Diff line number Diff line
@@ -261,6 +261,14 @@ struct dmcu *dcn10_dmcu_create( 
	const struct dce_dmcu_shift *dmcu_shift,

	const struct dce_dmcu_mask *dmcu_mask);



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

struct dmcu *dcn20_dmcu_create(

	struct dc_context *ctx,

	const struct dce_dmcu_registers *regs,

	const struct dce_dmcu_shift *dmcu_shift,

	const struct dce_dmcu_mask *dmcu_mask);

#endif



void dce_dmcu_destroy(struct dmcu **dmcu);



static const uint32_t abm_gain_stepsize = 0x0060;

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+127 −0
Original line number Diff line number Diff line
@@ -199,6 +199,70 @@ 
	SR(DC_IP_REQUEST_CNTL), \

	BL_REG_LIST()



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

#define HWSEQ_DCN2_REG_LIST()\

	HWSEQ_DCN_REG_LIST(), \

	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \

	HWSEQ_PHYPLL_REG_LIST(OTG), \

	SR(MICROSECOND_TIME_BASE_DIV), \

	SR(MILLISECOND_TIME_BASE_DIV), \

	SR(DISPCLK_FREQ_CHANGE_CNTL), \

	SR(RBBMIF_TIMEOUT_DIS), \

	SR(RBBMIF_TIMEOUT_DIS_2), \

	SR(DCHUBBUB_CRC_CTRL), \

	SR(DPP_TOP0_DPP_CRC_CTRL), \

	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \

	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \

	SR(MPC_CRC_CTRL), \

	SR(MPC_CRC_RESULT_GB), \

	SR(MPC_CRC_RESULT_C), \

	SR(MPC_CRC_RESULT_AR), \

	SR(DOMAIN0_PG_CONFIG), \

	SR(DOMAIN1_PG_CONFIG), \

	SR(DOMAIN2_PG_CONFIG), \

	SR(DOMAIN3_PG_CONFIG), \

	SR(DOMAIN4_PG_CONFIG), \

	SR(DOMAIN5_PG_CONFIG), \

	SR(DOMAIN6_PG_CONFIG), \

	SR(DOMAIN7_PG_CONFIG), \

	SR(DOMAIN8_PG_CONFIG), \

	SR(DOMAIN9_PG_CONFIG), \

	SR(DOMAIN10_PG_CONFIG), \

	SR(DOMAIN11_PG_CONFIG), \

	SR(DOMAIN16_PG_CONFIG), \

	SR(DOMAIN17_PG_CONFIG), \

	SR(DOMAIN18_PG_CONFIG), \

	SR(DOMAIN19_PG_CONFIG), \

	SR(DOMAIN20_PG_CONFIG), \

	SR(DOMAIN21_PG_CONFIG), \

	SR(DOMAIN0_PG_STATUS), \

	SR(DOMAIN1_PG_STATUS), \

	SR(DOMAIN2_PG_STATUS), \

	SR(DOMAIN3_PG_STATUS), \

	SR(DOMAIN4_PG_STATUS), \

	SR(DOMAIN5_PG_STATUS), \

	SR(DOMAIN6_PG_STATUS), \

	SR(DOMAIN7_PG_STATUS), \

	SR(DOMAIN8_PG_STATUS), \

	SR(DOMAIN9_PG_STATUS), \

	SR(DOMAIN10_PG_STATUS), \

	SR(DOMAIN11_PG_STATUS), \

	SR(DOMAIN16_PG_STATUS), \

	SR(DOMAIN17_PG_STATUS), \

	SR(DOMAIN18_PG_STATUS), \

	SR(DOMAIN19_PG_STATUS), \

	SR(DOMAIN20_PG_STATUS), \

	SR(DOMAIN21_PG_STATUS), \

	SR(D1VGA_CONTROL), \

	SR(D2VGA_CONTROL), \

	SR(D3VGA_CONTROL), \

	SR(D4VGA_CONTROL), \

	SR(D5VGA_CONTROL), \

	SR(D6VGA_CONTROL), \

	SR(DC_IP_REQUEST_CNTL), \

	BL_REG_LIST()

#endif



struct dce_hwseq_registers {



		/* Backlight registers */
@@ -453,6 +517,69 @@ struct dce_hwseq_registers { 
	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \

	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \

	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \

	HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \

	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)

#endif



#define HWSEQ_REG_FIELD_LIST(type) \

	type DCFE_CLOCK_ENABLE; \

	type DCFEV_CLOCK_ENABLE; \

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+41 −1
Original line number Diff line number Diff line
@@ -666,7 +666,26 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 


	/* update AVI info frame (HDMI, DP)*/

	/* TODO: FPGA may change to hwss.update_info_frame */

	dce110_update_info_frame(pipe_ctx);



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL &&

			pipe_ctx->plane_res.hubp != NULL) {

		if (pipe_ctx->stream->dmdata_address.quad_part != 0) {

			/* if using dynamic meta, don't set up generic infopackets */

			pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;

			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(

					pipe_ctx->stream_res.stream_enc,

					true, pipe_ctx->plane_res.hubp->inst,

					dc_is_dp_signal(pipe_ctx->stream->signal) ?

							dmdata_dp : dmdata_hdmi);

		} else

			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(

					pipe_ctx->stream_res.stream_enc,

					false, pipe_ctx->plane_res.hubp->inst,

					dc_is_dp_signal(pipe_ctx->stream->signal) ?

							dmdata_dp : dmdata_hdmi);

	}

#endif



	/* enable early control to avoid corruption on DP monitor*/

	active_total_with_borders =
@@ -951,6 +970,10 @@ static void set_pme_wa_enable_by_version(struct dc *dc) 
	if (pp_smu) {

		if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable)

			pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx));

#ifdef CONFIG_DRM_AMD_DC_DCN2_0

		else if (pp_smu->ctx.ver == PP_SMU_VER_NV && pp_smu->nv_funcs.set_pme_wa_enable)

			pp_smu->nv_funcs.set_pme_wa_enable(&(pp_smu->ctx));

#endif

	}

}
@@ -1337,6 +1360,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
	struct dc_stream_state *stream = pipe_ctx->stream;

	struct drr_params params = {0};

	unsigned int event_triggers = 0;

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);

#endif



	if (dc->hwss.disable_stream_gating) {

		dc->hwss.disable_stream_gating(dc, pipe_ctx);
@@ -1402,6 +1428,20 @@ static enum dc_status apply_single_controller_ctx_to_hw( 
		pipe_ctx->stream_res.opp,

		&stream->bit_depth_params,

		&stream->clamping);

#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

	if (odm_pipe) {

		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(

				odm_pipe->stream_res.opp,

				COLOR_SPACE_YCBCR601,

				stream->timing.display_color_depth,

				stream->signal);



		odm_pipe->stream_res.opp->funcs->opp_program_fmt(

				odm_pipe->stream_res.opp,

				&stream->bit_depth_params,

				&stream->clamping);

	}

#endif



	if (!stream->dpms_off)

		core_link_enable_stream(context, pipe_ctx);