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Commit 7ec2c73b authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Check the CPU cached value in HWS of seqno after waking the waiter 



If we have multiple waiters, we may find that many complete on the same
wake up. If we first inspect the seqno from the CPU cache, we may reduce
the number of heavyweight coherent seqno reads we require.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-13-git-send-email-chris@chris-wilson.co.uk
parent f8973c21

drivers/gpu/drm/i915/i915_drv.h

+10 −4
Original line number Diff line number Diff line
@@ -3988,6 +3988,12 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) 
{

	struct intel_engine_cs *engine = req->engine;



	/* Before we do the heavier coherent read of the seqno,

	 * check the value (hopefully) in the CPU cacheline.

	 */

	if (i915_gem_request_completed(req))

		return true;



	/* Ensure our read of the seqno is coherent so that we

	 * do not "miss an interrupt" (i.e. if this is the last

	 * request and the seqno write from the GPU is not visible
@@ -3999,11 +4005,11 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) 
	 * but it is easier and safer to do it every time the waiter

	 * is woken.

	 */

	if (engine->irq_seqno_barrier)

	if (engine->irq_seqno_barrier) {

		engine->irq_seqno_barrier(engine);



		if (i915_gem_request_completed(req))

			return true;

	}



	/* We need to check whether any gpu reset happened in between

	 * the request being submitted and now. If a reset has occurred,