Commit 7df54dbe authored Nov 20, 2018 by Andrea Merello Committed by Vinod Koul Jan 07, 2019

dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property



The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

parent 5c094d4c

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -41,6 +41,10 @@ Optional properties:
		- xlnx,include-sg: Tells configured for Scatter-mode in
		the hardware.
		Optional properties for AXI DMA:
		- xlnx,sg-length-width: Should be set to the width in bits of the length
		register as configured in h/w. Takes values {8...26}. If the property
		is missing or invalid then the default value 23 is used. This is the
		maximum value that is supported by all IP versions.
		- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
		Optional properties for VDMA:
		- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.