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Commit 7d7355f5 authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
Browse files

sh_eth: Ensure proper ordering of descriptor active bit write/read 



When submitting a DMA descriptor, the active bit must be written last.
When reading a completed DMA descriptor, the active bit must be read
first.

Add memory barriers to ensure that this ordering is maintained.

Signed-off-by: default avatarBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent eee617a1

drivers/net/ethernet/renesas/sh_eth.c

+6 −0
Original line number Diff line number Diff line
@@ -1410,6 +1410,8 @@ static int sh_eth_txfree(struct net_device *ndev) 
		txdesc = &mdp->tx_ring[entry];

		if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))

			break;

		/* TACT bit must be checked before all the following reads */

		rmb();

		/* Free the original skb. */

		if (mdp->tx_skbuff[entry]) {

			dma_unmap_single(&ndev->dev, txdesc->addr,
@@ -1447,6 +1449,8 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 
	limit = boguscnt;

	rxdesc = &mdp->rx_ring[entry];

	while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {

		/* RACT bit must be checked before all the following reads */

		rmb();

		desc_status = edmac_to_cpu(mdp, rxdesc->status);

		pkt_len = rxdesc->frame_length;
@@ -1526,6 +1530,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 
			skb_checksum_none_assert(skb);

			rxdesc->addr = dma_addr;

		}

		wmb(); /* RACT bit must be set after all the above writes */

		if (entry >= mdp->num_rx_ring - 1)

			rxdesc->status |=

				cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
@@ -2195,6 +2200,7 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 
	}

	txdesc->buffer_length = skb->len;



	wmb(); /* TACT bit must be set after all the above writes */

	if (entry >= mdp->num_tx_ring - 1)

		txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);

	else