Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7d4a3c93 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Greg Kroah-Hartman
Browse files

ARM: iop32x: offset IRQ numbers by 1 



commit 9d67412f24cc3a2c05f35f7c856addb07a2960ce upstream.

iop32x is one of the last platforms to use IRQ 0, and this has apparently
stopped working in a 2014 cleanup without anyone noticing. This interrupt
is used for the DMA engine, so most likely this has not actually worked
in the past 7 years, but it's also not essential for using this board.

I'm splitting out this change from my GENERIC_IRQ_MULTI_HANDLER
conversion so it can be backported if anyone cares.

Fixes: a71b092a ("ARM: Convert handle_IRQ to use __handle_domain_irq")
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
[ardb: take +1 offset into account in mask/unmask and init as well]
Signed-off-by: default avatarArd Biesheuvel <ardb@kernel.org>
Tested-by: default avatarMarc Zyngier <maz@kernel.org>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d727fd32

arch/arm/mach-iop32x/include/mach/entry-macro.S

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
	mrc     p6, 0, \irqstat, c8, c0, 0	@ Read IINTSRC

	cmp     \irqstat, #0

	clzne   \irqnr, \irqstat

	rsbne   \irqnr, \irqnr, #31

	rsbne   \irqnr, \irqnr, #32

	.endm



	.macro arch_ret_to_user, tmp1, tmp2

arch/arm/mach-iop32x/include/mach/irqs.h

+1 −1
Original line number Diff line number Diff line
@@ -9,6 +9,6 @@ 
#ifndef __IRQS_H

#define __IRQS_H



#define NR_IRQS			32

#define NR_IRQS			33



#endif

arch/arm/mach-iop32x/irq.c

+3 −3
Original line number Diff line number Diff line
@@ -32,14 +32,14 @@ static void intstr_write(u32 val) 
static void

iop32x_irq_mask(struct irq_data *d)

{

	iop32x_mask &= ~(1 << d->irq);

	iop32x_mask &= ~(1 << (d->irq - 1));

	intctl_write(iop32x_mask);

}



static void

iop32x_irq_unmask(struct irq_data *d)

{

	iop32x_mask |= 1 << d->irq;

	iop32x_mask |= 1 << (d->irq - 1);

	intctl_write(iop32x_mask);

}
@@ -65,7 +65,7 @@ void __init iop32x_init_irq(void) 
	    machine_is_em7210())

		*IOP3XX_PCIIRSR = 0x0f;



	for (i = 0; i < NR_IRQS; i++) {

	for (i = 1; i < NR_IRQS; i++) {

		irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);

		irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);

	}

arch/arm/mach-iop32x/irqs.h

+32 −28
Original line number Diff line number Diff line
@@ -7,36 +7,40 @@ 
#ifndef __IOP32X_IRQS_H

#define __IOP32X_IRQS_H



/* Interrupts in Linux start at 1, hardware starts at 0 */



#define IOP_IRQ(x) ((x) + 1)



/*

 * IOP80321 chipset interrupts

 */

#define IRQ_IOP32X_DMA0_EOT	0

#define IRQ_IOP32X_DMA0_EOC	1

#define IRQ_IOP32X_DMA1_EOT	2

#define IRQ_IOP32X_DMA1_EOC	3

#define IRQ_IOP32X_AA_EOT	6

#define IRQ_IOP32X_AA_EOC	7

#define IRQ_IOP32X_CORE_PMON	8

#define IRQ_IOP32X_TIMER0	9

#define IRQ_IOP32X_TIMER1	10

#define IRQ_IOP32X_I2C_0	11

#define IRQ_IOP32X_I2C_1	12

#define IRQ_IOP32X_MESSAGING	13

#define IRQ_IOP32X_ATU_BIST	14

#define IRQ_IOP32X_PERFMON	15

#define IRQ_IOP32X_CORE_PMU	16

#define IRQ_IOP32X_BIU_ERR	17

#define IRQ_IOP32X_ATU_ERR	18

#define IRQ_IOP32X_MCU_ERR	19

#define IRQ_IOP32X_DMA0_ERR	20

#define IRQ_IOP32X_DMA1_ERR	21

#define IRQ_IOP32X_AA_ERR	23

#define IRQ_IOP32X_MSG_ERR	24

#define IRQ_IOP32X_SSP		25

#define IRQ_IOP32X_XINT0	27

#define IRQ_IOP32X_XINT1	28

#define IRQ_IOP32X_XINT2	29

#define IRQ_IOP32X_XINT3	30

#define IRQ_IOP32X_HPI		31

#define IRQ_IOP32X_DMA0_EOT	IOP_IRQ(0)

#define IRQ_IOP32X_DMA0_EOC	IOP_IRQ(1)

#define IRQ_IOP32X_DMA1_EOT	IOP_IRQ(2)

#define IRQ_IOP32X_DMA1_EOC	IOP_IRQ(3)

#define IRQ_IOP32X_AA_EOT	IOP_IRQ(6)

#define IRQ_IOP32X_AA_EOC	IOP_IRQ(7)

#define IRQ_IOP32X_CORE_PMON	IOP_IRQ(8)

#define IRQ_IOP32X_TIMER0	IOP_IRQ(9)

#define IRQ_IOP32X_TIMER1	IOP_IRQ(10)

#define IRQ_IOP32X_I2C_0	IOP_IRQ(11)

#define IRQ_IOP32X_I2C_1	IOP_IRQ(12)

#define IRQ_IOP32X_MESSAGING	IOP_IRQ(13)

#define IRQ_IOP32X_ATU_BIST	IOP_IRQ(14)

#define IRQ_IOP32X_PERFMON	IOP_IRQ(15)

#define IRQ_IOP32X_CORE_PMU	IOP_IRQ(16)

#define IRQ_IOP32X_BIU_ERR	IOP_IRQ(17)

#define IRQ_IOP32X_ATU_ERR	IOP_IRQ(18)

#define IRQ_IOP32X_MCU_ERR	IOP_IRQ(19)

#define IRQ_IOP32X_DMA0_ERR	IOP_IRQ(20)

#define IRQ_IOP32X_DMA1_ERR	IOP_IRQ(21)

#define IRQ_IOP32X_AA_ERR	IOP_IRQ(23)

#define IRQ_IOP32X_MSG_ERR	IOP_IRQ(24)

#define IRQ_IOP32X_SSP		IOP_IRQ(25)

#define IRQ_IOP32X_XINT0	IOP_IRQ(27)

#define IRQ_IOP32X_XINT1	IOP_IRQ(28)

#define IRQ_IOP32X_XINT2	IOP_IRQ(29)

#define IRQ_IOP32X_XINT3	IOP_IRQ(30)

#define IRQ_IOP32X_HPI		IOP_IRQ(31)



#endif