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Commit 7d3f6b53 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

ARM: dts: meson8: add the Mali-450 MP6 GPU 



Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the
latter inherits meson8.dtsi).
These SoCs have a Mali-450 GPU with six pixel processors. The OPP table
is taken from the 3.10 vendor kernel which uses the following table:
  FCLK_DEV7 | 1,     /* 182.1 Mhz */
  FCLK_DEV4 | 1,     /* 318.7 Mhz */
  FCLK_DEV3 | 1,     /* 425 Mhz */
  FCLK_DEV5 | 0,     /* 510 Mhz */
  FCLK_DEV4 | 0,     /* 637.5 Mhz */
This describes the mux (FCLK_DEVx) and a 0-based divider in the clock
controller. "FCLK" is "fixed_pll" which is running at 2550MHz.
The "turbo" setting is described by "turbo_clock = 4" where 4 is the
index of the table above.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent 5938f2c8

arch/arm/boot/dts/meson8.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -166,6 +166,32 @@ 
		};

	};



	gpu_opp_table: gpu-opp-table {

		compatible = "operating-points-v2";



		opp-182150000 {

			opp-hz = /bits/ 64 <182150000>;

			opp-microvolt = <1150000>;

		};

		opp-318750000 {

			opp-hz = /bits/ 64 <318750000>;

			opp-microvolt = <1150000>;

		};

		opp-425000000 {

			opp-hz = /bits/ 64 <425000000>;

			opp-microvolt = <1150000>;

		};

		opp-510000000 {

			opp-hz = /bits/ 64 <510000000>;

			opp-microvolt = <1150000>;

		};

		opp-637500000 {

			opp-hz = /bits/ 64 <637500000>;

			opp-microvolt = <1150000>;

			turbo-mode;

		};

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
@@ -208,6 +234,38 @@ 
		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0xd0000000 0x200000>;



		mali: gpu@c0000 {

			compatible = "amlogic,meson8-mali", "arm,mali-450";

			reg = <0xc0000 0x40000>;

			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "gp", "gpmmu", "pp", "pmu",

					  "pp0", "ppmmu0", "pp1", "ppmmu1",

					  "pp2", "ppmmu2", "pp4", "ppmmu4",

					  "pp5", "ppmmu5", "pp6", "ppmmu6";

			resets = <&reset RESET_MALI>;

			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;

			clock-names = "bus", "core";

			operating-points-v2 = <&gpu_opp_table>;

			switch-delay = <0xffff>;

		};

	};

}; /* end of / */