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Commit 7d318d77 authored by Andi Kleen's avatar Andi Kleen Committed by Linus Torvalds
Browse files

[PATCH] Fix up TLB flush filter disabling 



I checked with AMD and they requested to only disable it for family 15.
Also disable it for i386 too. And some style fixes.

Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 5acbc5cb

arch/i386/kernel/cpu/amd.c

+16 −0
Original line number Diff line number Diff line
@@ -28,6 +28,22 @@ static void __init init_amd(struct cpuinfo_x86 *c) 
	int mbytes = num_physpages >> (20-PAGE_SHIFT);

	int r;



#ifdef CONFIG_SMP

	unsigned long value;



	/* Disable TLB flush filter by setting HWCR.FFDIS on K8

	 * bit 6 of msr C001_0015

	 *

	 * Errata 63 for SH-B3 steppings

	 * Errata 122 for all steppings (F+ have it disabled by default)

	 */

	if (c->x86 == 15) {

		rdmsrl(MSR_K7_HWCR, value);

		value |= 1 << 6;

		wrmsrl(MSR_K7_HWCR, value);

	}

#endif



	/*

	 *	FIXME: We should handle the K5 here. Set up the write

	 *	range and also turn on MSR 83 bits 4 and 31 (write alloc,

arch/x86_64/kernel/setup.c

+12 −10
Original line number Diff line number Diff line
@@ -831,8 +831,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c) 
#endif

}



#define HWCR 0xc0010015



static int __init init_amd(struct cpuinfo_x86 *c)

{

	int r;
@@ -841,14 +839,18 @@ static int __init init_amd(struct cpuinfo_x86 *c) 
#ifdef CONFIG_SMP

	unsigned long value;



	// Disable TLB flush filter by setting HWCR.FFDIS:

	// bit 6 of msr C001_0015

	//

	// Errata 63 for SH-B3 steppings

	// Errata 122 for all(?) steppings

	rdmsrl(HWCR, value);

	/*

	 * Disable TLB flush filter by setting HWCR.FFDIS on K8

	 * bit 6 of msr C001_0015

 	 *

	 * Errata 63 for SH-B3 steppings

	 * Errata 122 for all steppings (F+ have it disabled by default)

	 */

	if (c->x86 == 15) {

		rdmsrl(MSR_K8_HWCR, value);

		value |= 1 << 6;

	wrmsrl(HWCR, value);

		wrmsrl(MSR_K8_HWCR, value);

	}

#endif



	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;

include/asm-x86_64/msr.h

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ static inline unsigned int cpuid_edx(unsigned int op) 
#define MSR_K8_TOP_MEM1		   0xC001001A

#define MSR_K8_TOP_MEM2		   0xC001001D

#define MSR_K8_SYSCFG		   0xC0010010

#define MSR_K8_HWCR		   0xC0010015



/* K6 MSRs */

#define MSR_K6_EFER			0xC0000080