Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7d0d0df0 authored by Sujith's avatar Sujith Committed by John W. Linville
Browse files

ath9k_hw: Use buffered register writes 



This patch adds macros at certain places
which could be optimized for multiple register writes.

The performance of ath9k_htc improves considerably,
especially reducing the latency involved in a scan run.

Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 6819d57f

drivers/net/wireless/ath/ath9k/ani.c

+23 −0
Original line number Diff line number Diff line
@@ -79,11 +79,17 @@ static void ath9k_ani_restart(struct ath_hw *ah) 
		  "Writing ofdmbase=%u   cckbase=%u\n",

		  aniState->ofdmPhyErrBase,

		  aniState->cckPhyErrBase);



	ENABLE_REGWRITE_BUFFER(ah);



	REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);

	REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);

	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);

	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);



	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);



	aniState->ofdmPhyErrCount = 0;
@@ -357,8 +363,14 @@ void ath9k_ani_reset(struct ath_hw *ah) 
	ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &

			     ~ATH9K_RX_FILTER_PHYERR);

	ath9k_ani_restart(ah);



	ENABLE_REGWRITE_BUFFER(ah);



	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);

	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

}



void ath9k_hw_ani_monitor(struct ath_hw *ah,
@@ -456,6 +468,8 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) 


	ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);



	ENABLE_REGWRITE_BUFFER(ah);



	REG_WRITE(ah, AR_FILT_OFDM, 0);

	REG_WRITE(ah, AR_FILT_CCK, 0);

	REG_WRITE(ah, AR_MIBC,
@@ -463,6 +477,9 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) 
		  & 0x0f);

	REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);

	REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

}



/* Freeze the MIB counters, get the stats and then clear them */
@@ -626,8 +643,14 @@ void ath9k_hw_ani_init(struct ath_hw *ah) 
	ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",

		  ah->ani[0].cckPhyErrBase);



	ENABLE_REGWRITE_BUFFER(ah);



	REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);

	REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);



	ath9k_enable_mib_counters(ah);



	ah->aniperiod = ATH9K_ANI_PERIOD;

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+28 −0
Original line number Diff line number Diff line
@@ -590,10 +590,14 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 
	rx_chainmask = ah->rxchainmask;

	tx_chainmask = ah->txchainmask;



	ENABLE_REGWRITE_BUFFER(ah);



	switch (rx_chainmask) {

	case 0x5:

		DISABLE_REGWRITE_BUFFER(ah);

		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,

			    AR_PHY_SWAP_ALT_CHAIN);

		ENABLE_REGWRITE_BUFFER(ah);

	case 0x3:

		if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {

			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -611,6 +615,10 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 
	}



	REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);



	if (tx_chainmask == 0x5) {

		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,

			    AR_PHY_SWAP_ALT_CHAIN);
@@ -689,8 +697,13 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 


	ath9k_hw_set11nmac2040(ah);



	ENABLE_REGWRITE_BUFFER(ah);



	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);

	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

}
@@ -773,6 +786,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, 


	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);



	ENABLE_REGWRITE_BUFFER(ah);



	for (i = 0; i < ah->iniModes.ia_rows; i++) {

		u32 reg = INI_RA(&ah->iniModes, i, 0);

		u32 val = INI_RA(&ah->iniModes, i, modesIndex);
@@ -790,6 +805,9 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, 
		DO_DELAY(regWrites);

	}



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);



	if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))

		REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
@@ -801,6 +819,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, 
		REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,

				modesIndex, regWrites);



	ENABLE_REGWRITE_BUFFER(ah);



	/* Write common array parameters */

	for (i = 0; i < ah->iniCommon.ia_rows; i++) {

		u32 reg = INI_RA(&ah->iniCommon, i, 0);
@@ -816,6 +836,9 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, 
		DO_DELAY(regWrites);

	}



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);



	if (AR_SREV_9271(ah)) {

		if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)

			REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
@@ -1303,6 +1326,8 @@ static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) 
		udelay(50);

	}



	ENABLE_REGWRITE_BUFFER(ah);



	for (i = 0; i < NUM_NF_READINGS; i++) {

		if (chainmask & (1 << i)) {

			val = REG_READ(ah, ar5416_cca_regs[i]);
@@ -1311,6 +1336,9 @@ static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) 
			REG_WRITE(ah, ar5416_cca_regs[i], val);

		}

	}



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

}



void ar5008_hw_attach_phy_ops(struct ath_hw *ah)

drivers/net/wireless/ath/ath9k/ar9002_calib.c

+5 −0
Original line number Diff line number Diff line
@@ -527,6 +527,8 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset) 
		ah->pacal_info.prev_offset = regVal;

	}



	ENABLE_REGWRITE_BUFFER(ah);



	regVal = REG_READ(ah, 0x7834);

	regVal |= 0x1;

	REG_WRITE(ah, 0x7834, regVal);
@@ -536,6 +538,9 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset) 


	for (i = 0; i < ARRAY_SIZE(regList); i++)

		REG_WRITE(ah, regList[i][0], regList[i][1]);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

}



static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)

drivers/net/wireless/ath/ath9k/ar9002_hw.c

+6 −1
Original line number Diff line number Diff line
@@ -488,10 +488,15 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah) 
	u32 val;

	int i;



	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);

	ENABLE_REGWRITE_BUFFER(ah);



	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);

	for (i = 0; i < 8; i++)

		REG_WRITE(ah, AR_PHY(0x20), 0x00010000);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);



	val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;

	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

+5 −0
Original line number Diff line number Diff line
@@ -236,6 +236,8 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah, 


	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));



	ENABLE_REGWRITE_BUFFER(ah);



	newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |

			AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |

			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
@@ -411,6 +413,9 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah, 
		| (mask_p[47] << 2) | (mask_p[46] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

}



static void ar9002_olc_init(struct ath_hw *ah)