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Commit 7cabf491 authored by Varun Sethi's avatar Varun Sethi Committed by Joerg Roedel
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iommu/fsl: Add additional iommu attributes required by the PAMU driver. 



Added the following domain attributes for the FSL PAMU driver:
1. Added new iommu stash attribute, which allows setting of the
   LIODN specific stash id parameter through IOMMU API.
2. Added an attribute for enabling/disabling DMA to a particular
   memory window.
3. Added domain attribute to check for PAMUV1 specific constraints.

Signed-off-by: default avatarVarun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: default avatarJoerg Roedel <joro@8bytes.org>
parent bb917505

arch/powerpc/include/asm/fsl_pamu_stash.h

0 → 100644
+39 −0
Original line number Diff line number Diff line 
/*

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License, version 2, as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

 *

 * Copyright (C) 2013 Freescale Semiconductor, Inc.

 *

 */



#ifndef __FSL_PAMU_STASH_H

#define __FSL_PAMU_STASH_H



/* cache stash targets */

enum pamu_stash_target {

	PAMU_ATTR_CACHE_L1 = 1,

	PAMU_ATTR_CACHE_L2,

	PAMU_ATTR_CACHE_L3,

};



/*

 * This attribute allows configuring stashig specific parameters

 * in the PAMU hardware.

 */



struct pamu_stash_attribute {

	u32 	cpu;	/* cpu number */

	u32 	cache;	/* cache to stash to: L1,L2,L3 */

};



#endif  /* __FSL_PAMU_STASH_H */

include/linux/iommu.h

+16 −0
Original line number Diff line number Diff line
@@ -58,10 +58,26 @@ struct iommu_domain { 
#define IOMMU_CAP_CACHE_COHERENCY	0x1

#define IOMMU_CAP_INTR_REMAP		0x2	/* isolates device intrs */



/*

 * Following constraints are specifc to FSL_PAMUV1:

 *  -aperture must be power of 2, and naturally aligned

 *  -number of windows must be power of 2, and address space size

 *   of each window is determined by aperture size / # of windows

 *  -the actual size of the mapped region of a window must be power

 *   of 2 starting with 4KB and physical address must be naturally

 *   aligned.

 * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints.

 * The caller can invoke iommu_domain_get_attr to check if the underlying

 * iommu implementation supports these constraints.

 */



enum iommu_attr {

	DOMAIN_ATTR_GEOMETRY,

	DOMAIN_ATTR_PAGING,

	DOMAIN_ATTR_WINDOWS,

	DOMAIN_ATTR_FSL_PAMU_STASH,

	DOMAIN_ATTR_FSL_PAMU_ENABLE,

	DOMAIN_ATTR_FSL_PAMUV1,

	DOMAIN_ATTR_MAX,

};