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Commit 7c94bc82 authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
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drm/amdgpu: Setting doorbell range registers earlier 



HW doorbell writing routing policy: writing to doorbell
not in SDMA/IH/MM/ACV doorbell range will be routed to CP.
So CP doorbell routing depends on doorbell range setting
of above blocks. Setting doorbell range of above blocks
earlier (soc15_common_hw_init) to make sure CP doorbell
writing be routed to CP block.

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8987e2e2

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+0 −3
Original line number Diff line number Diff line
@@ -834,9 +834,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 
					OFFSET, ring->doorbell_index);

	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);

	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);

	adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,

					      ring->doorbell_index,

					      adev->doorbell_index.sdma_doorbell_range);



	sdma_v4_0_ring_set_wptr(ring);

drivers/gpu/drm/amd/amdgpu/soc15.c

+22 −0
Original line number Diff line number Diff line
@@ -966,6 +966,22 @@ static int soc15_common_sw_fini(void *handle) 
	return 0;

}



static void soc15_doorbell_range_init(struct amdgpu_device *adev)

{

	int i;

	struct amdgpu_ring *ring;



	for (i = 0; i < adev->sdma.num_instances; i++) {

		ring = &adev->sdma.instance[i].ring;

		adev->nbio_funcs->sdma_doorbell_range(adev, i,

			ring->use_doorbell, ring->doorbell_index,

			adev->doorbell_index.sdma_doorbell_range);

	}



	adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,

						adev->irq.ih.doorbell_index);

}



static int soc15_common_hw_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -978,6 +994,12 @@ static int soc15_common_hw_init(void *handle) 
	adev->nbio_funcs->init_registers(adev);

	/* enable the doorbell aperture */

	soc15_enable_doorbell_aperture(adev, true);

	/* HW doorbell routing policy: doorbell writing not

	 * in SDMA/IH/MM/ACV range will be routed to CP. So

	 * we need to init SDMA/IH/MM/ACV doorbell range prior

	 * to CP ip block init and ring test.

	 */

	soc15_doorbell_range_init(adev);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+0 −2
Original line number Diff line number Diff line
@@ -140,8 +140,6 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
						 ENABLE, 0);

	}

	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);

	adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,

					    adev->irq.ih.doorbell_index);



	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);

	tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,