Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7c7fba98 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-4.11-rc2' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Intel, amd and mxsfb fixes.

  These are the drm fixes I've collected for rc2. Mostly i915 GVT only
  fixes, along with a single EDID fix, some mxsfb fixes and a few minor
  amd fixes"

* tag 'drm-fixes-for-4.11-rc2' of git://people.freedesktop.org/~airlied/linux: (38 commits)
  drm: mxsfb: Implement drm_panel handling
  drm: mxsfb_crtc: Fix the framebuffer misplacement
  drm: mxsfb: Fix crash when provided invalid DT bindings
  drm: mxsfb: fix pixel clock polarity
  drm: mxsfb: use bus_format to determine LCD bus width
  drm/amdgpu: bump driver version for some new features
  drm/amdgpu: validate paramaters in the gem ioctl
  drm/amd/amdgpu: fix console deadlock if late init failed
  drm/i915/gvt: change some gvt_err to gvt_dbg_cmd
  drm/i915/gvt: protect RO and Rsvd bits of virtual vgpu configuration space
  drm/i915/gvt: handle workload lifecycle properly
  drm/edid: Add EDID_QUIRK_FORCE_8BPC quirk for Rotel RSX-1058
  drm/i915/gvt: fix an error for F_RO flag
  drm/i915/gvt: use pfn_valid for better checking
  drm/i915/gvt: set SFUSE_STRAP properly for vitual monitor detection
  drm/i915/gvt: fix an error for one register
  drm/i915/gvt: add more registers into handlers list
  drm/i915/gvt: have more registers with F_CMD_ACCESS flags set
  drm/i915/gvt: add some new MMIOs to cmd_access white list
  drm/i915/gvt: fix pcode mailbox write emulation of BDW
  ...
parents baeedc71 3f81e134

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+4 −1
Original line number Diff line number Diff line
@@ -2094,8 +2094,11 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) 
	}



	r = amdgpu_late_init(adev);

	if (r)

	if (r) {

		if (fbcon)

			console_unlock();

		return r;

	}



	/* pin cursors */

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -59,9 +59,10 @@ 
 * - 3.7.0 - Add support for VCE clock list packet

 * - 3.8.0 - Add support raster config init in the kernel

 * - 3.9.0 - Add support for memory query info about VRAM and GTT.

 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	9

#define KMS_DRIVER_MINOR	10

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+21 −0
Original line number Diff line number Diff line
@@ -202,6 +202,27 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 
	bool kernel = false;

	int r;



	/* reject invalid gem flags */

	if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |

				      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |

				      AMDGPU_GEM_CREATE_CPU_GTT_USWC |

				      AMDGPU_GEM_CREATE_VRAM_CLEARED|

				      AMDGPU_GEM_CREATE_SHADOW |

				      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {

		r = -EINVAL;

		goto error_unlock;

	}

	/* reject invalid gem domains */

	if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |

				 AMDGPU_GEM_DOMAIN_GTT |

				 AMDGPU_GEM_DOMAIN_VRAM |

				 AMDGPU_GEM_DOMAIN_GDS |

				 AMDGPU_GEM_DOMAIN_GWS |

				 AMDGPU_GEM_DOMAIN_OA)) {

		r = -EINVAL;

		goto error_unlock;

	}



	/* create a gem object to contain this object in */

	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |

	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {

drivers/gpu/drm/drm_edid.c

+3 −0
Original line number Diff line number Diff line
@@ -148,6 +148,9 @@ static const struct edid_quirk { 


	/* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */

	{ "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },



	/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/

	{ "ETR", 13896, EDID_QUIRK_FORCE_8BPC },

};



/*

drivers/gpu/drm/i915/gvt/cfg_space.c

+54 −3
Original line number Diff line number Diff line
@@ -41,6 +41,54 @@ enum { 
	INTEL_GVT_PCI_BAR_MAX,

};



/* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one

 * byte) byte by byte in standard pci configuration space. (not the full

 * 256 bytes.)

 */

static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {

	[PCI_COMMAND]		= 0xff, 0x07,

	[PCI_STATUS]		= 0x00, 0xf9, /* the only one RW1C byte */

	[PCI_CACHE_LINE_SIZE]	= 0xff,

	[PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,

	[PCI_ROM_ADDRESS]	= 0x01, 0xf8, 0xff, 0xff,

	[PCI_INTERRUPT_LINE]	= 0xff,

};



/**

 * vgpu_pci_cfg_mem_write - write virtual cfg space memory

 *

 * Use this function to write virtual cfg space memory.

 * For standard cfg space, only RW bits can be changed,

 * and we emulates the RW1C behavior of PCI_STATUS register.

 */

static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,

				   u8 *src, unsigned int bytes)

{

	u8 *cfg_base = vgpu_cfg_space(vgpu);

	u8 mask, new, old;

	int i = 0;



	for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {

		mask = pci_cfg_space_rw_bmp[off + i];

		old = cfg_base[off + i];

		new = src[i] & mask;



		/**

		 * The PCI_STATUS high byte has RW1C bits, here

		 * emulates clear by writing 1 for these bits.

		 * Writing a 0b to RW1C bits has no effect.

		 */

		if (off + i == PCI_STATUS + 1)

			new = (~new & old) & mask;



		cfg_base[off + i] = (old & ~mask) | new;

	}



	/* For other configuration space directly copy as it is. */

	if (i < bytes)

		memcpy(cfg_base + off + i, src + i, bytes - i);

}



/**

 * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read

 *
@@ -123,7 +171,7 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu, 
	u8 changed = old ^ new;

	int ret;



	memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);

	vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);

	if (!(changed & PCI_COMMAND_MEMORY))

		return 0;
@@ -237,6 +285,9 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
{

	int ret;



	if (vgpu->failsafe)

		return 0;



	if (WARN_ON(bytes > 4))

		return -EINVAL;
@@ -274,10 +325,10 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
		if (ret)

			return ret;



		memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);

		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);

		break;

	default:

		memcpy(vgpu_cfg_space(vgpu) + offset, p_data, bytes);

		vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);

		break;

	}

	return 0;