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Commit 7c5c2c2d authored by Andre Przywara's avatar Andre Przywara Committed by Linus Walleij
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pinctrl: sunxi: Fix A64 UART mux value 



To use pin PF4 as the RX signal of UART0, we have to write 0b011 into
the respective pin controller register.
Fix the wrong value we had in our table so far.

Fixes: 96851d39 ("drivers: pinctrl: add driver for Allwinner A64 SoC")
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 6ad4cc8d

drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c

+1 −1
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_pins[] = { 
		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */

		  SUNXI_FUNCTION(0x4, "uart0")),	/* RX */

		  SUNXI_FUNCTION(0x3, "uart0")),	/* RX */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),