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Commit 7c12aa08 authored by Lendacky, Thomas's avatar Lendacky, Thomas Committed by David S. Miller
Browse files

amd-xgbe: Move the PHY support into amd-xgbe 



The AMD XGBE device is intended to work with a specific integrated PHY
and that PHY is not meant to be a standalone PHY for use by other
devices. As such this patch removes the phylib driver and implements
the PHY support in the amd-xgbe driver (the majority of the logic from
the phylib driver is moved into the amd-xgbe driver).

Update the driver version to 1.0.1.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7d9ca345

Documentation/devicetree/bindings/net/amd-xgbe-phy.txt

deleted100644 → 0
+0 −48
Original line number Diff line number Diff line 
* AMD 10GbE PHY driver (amd-xgbe-phy)



Required properties:

- compatible: Should be "amd,xgbe-phy-seattle-v1a" and

  "ethernet-phy-ieee802.3-c45"

- reg: Address and length of the register sets for the device

   - SerDes Rx/Tx registers

   - SerDes integration registers (1/2)

   - SerDes integration registers (2/2)

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the amd-xgbe-phy interrupt.



Optional properties:

- amd,speed-set: Speed capabilities of the device

    0 - 1GbE and 10GbE (default)

    1 - 2.5GbE and 10GbE



The following optional properties are represented by an array with each

value corresponding to a particular speed. The first array value represents

the setting for the 1GbE speed, the second value for the 2.5GbE speed and

the third value for the 10GbE speed.  All three values are required if the

property is used.

- amd,serdes-blwc: Baseline wandering correction enablement

    0 - Off

    1 - On

- amd,serdes-cdr-rate: CDR rate speed selection

- amd,serdes-pq-skew: PQ (data sampling) skew

- amd,serdes-tx-amp: TX amplitude boost

- amd,serdes-dfe-tap-config: DFE taps available to run

- amd,serdes-dfe-tap-enable: DFE taps to enable



Example:

	xgbe_phy@e1240800 {

		compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45";

		reg = <0 0xe1240800 0 0x00400>,

		      <0 0xe1250000 0 0x00060>,

		      <0 0xe1250080 0 0x00004>;

		interrupt-parent = <&gic>;

		interrupts = <0 323 4>;

		amd,speed-set = <0>;

		amd,serdes-blwc = <1>, <1>, <0>;

		amd,serdes-cdr-rate = <2>, <2>, <7>;

		amd,serdes-pq-skew = <10>, <10>, <30>;

		amd,serdes-tx-amp = <15>, <15>, <10>;

		amd,serdes-dfe-tap-config = <3>, <3>, <1>;

		amd,serdes-dfe-tap-enable = <0>, <0>, <127>;

	};

Documentation/devicetree/bindings/net/amd-xgbe.txt

+48 −3
Original line number Diff line number Diff line 
* AMD 10GbE driver (amd-xgbe)



Required properties:

Required properties (ethernet device):

- compatible: Should be "amd,xgbe-seattle-v1a"

- reg: Address and length of the register sets for the device

   - MAC registers
@@ -22,7 +22,7 @@ Required properties: 
- phy-handle: See ethernet.txt file in the same directory

- phy-mode: See ethernet.txt file in the same directory



Optional properties:

Optional properties (ethernet device):

- mac-address: mac address to be assigned to the device. Can be overridden

  by UEFI.

- dma-coherent: Present if dma operations are coherent
@@ -30,6 +30,35 @@ Optional properties: 
  a unique interrupt for each DMA channel - this requires an additional

  interrupt be configured for each DMA channel



Required properties (phy device):

- compatible: Should be "amd,xgbe-phy-seattle-v1a"

- reg: Address and length of the register sets for the device

   - SerDes Rx/Tx registers

   - SerDes integration registers (1/2)

   - SerDes integration registers (2/2)

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the amd-xgbe-phy interrupt.



Optional properties (phy device):

- amd,speed-set: Speed capabilities of the device

    0 - 1GbE and 10GbE (default)

    1 - 2.5GbE and 10GbE



The following optional properties are represented by an array with each

value corresponding to a particular speed. The first array value represents

the setting for the 1GbE speed, the second value for the 2.5GbE speed and

the third value for the 10GbE speed.  All three values are required if the

property is used.

- amd,serdes-blwc: Baseline wandering correction enablement

    0 - Off

    1 - On

- amd,serdes-cdr-rate: CDR rate speed selection

- amd,serdes-pq-skew: PQ (data sampling) skew

- amd,serdes-tx-amp: TX amplitude boost

- amd,serdes-dfe-tap-config: DFE taps available to run

- amd,serdes-dfe-tap-enable: DFE taps to enable



Example:

	xgbe@e0700000 {

		compatible = "amd,xgbe-seattle-v1a";
@@ -41,7 +70,23 @@ Example: 
		amd,per-channel-interrupt;

		clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;

		clock-names = "dma_clk", "ptp_clk";

		phy-handle = <&phy>;

		phy-handle = <&xgbe_phy>;

		phy-mode = "xgmii";

		mac-address = [ 02 a1 a2 a3 a4 a5 ];

	};



	xgbe_phy@e1240800 {

		compatible = "amd,xgbe-phy-seattle-v1a";

		reg = <0 0xe1240800 0 0x00400>,

		      <0 0xe1250000 0 0x00060>,

		      <0 0xe1250080 0 0x00004>;

		interrupt-parent = <&gic>;

		interrupts = <0 323 4>;

		amd,speed-set = <0>;

		amd,serdes-blwc = <1>, <1>, <0>;

		amd,serdes-cdr-rate = <2>, <2>, <7>;

		amd,serdes-pq-skew = <10>, <10>, <30>;

		amd,serdes-tx-amp = <15>, <15>, <10>;

		amd,serdes-dfe-tap-config = <3>, <3>, <1>;

		amd,serdes-dfe-tap-enable = <0>, <0>, <127>;

	};

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -652,7 +652,6 @@ M: Tom Lendacky <thomas.lendacky@amd.com> 
L:	netdev@vger.kernel.org

S:	Supported

F:	drivers/net/ethernet/amd/xgbe/

F:	drivers/net/phy/amd-xgbe-phy.c



AMS (Apple Motion Sensor) DRIVER

M:	Michael Hanselmann <linux-kernel@hansmi.ch>

drivers/net/ethernet/amd/Kconfig

+1 −3
Original line number Diff line number Diff line
@@ -179,10 +179,8 @@ config SUNLANCE 


config AMD_XGBE

	tristate "AMD 10GbE Ethernet driver"

	depends on (OF_NET || ACPI) && HAS_IOMEM && HAS_DMA

	depends on ((OF_NET && OF_ADDRESS) || ACPI) && HAS_IOMEM && HAS_DMA

	depends on ARM64 || COMPILE_TEST

	select PHYLIB

	select AMD_XGBE_PHY

	select BITREVERSE

	select CRC32

	select PTP_1588_CLOCK

drivers/net/ethernet/amd/xgbe/xgbe-common.h

+155 −0
Original line number Diff line number Diff line
@@ -857,6 +857,48 @@ 
 */

#define PCS_MMD_SELECT			0xff



/* SerDes integration register offsets */

#define SIR0_KR_RT_1			0x002c

#define SIR0_STATUS			0x0040

#define SIR1_SPEED			0x0000



/* SerDes integration register entry bit positions and sizes */

#define SIR0_KR_RT_1_RESET_INDEX	11

#define SIR0_KR_RT_1_RESET_WIDTH	1

#define SIR0_STATUS_RX_READY_INDEX	0

#define SIR0_STATUS_RX_READY_WIDTH	1

#define SIR0_STATUS_TX_READY_INDEX	8

#define SIR0_STATUS_TX_READY_WIDTH	1

#define SIR1_SPEED_CDR_RATE_INDEX	12

#define SIR1_SPEED_CDR_RATE_WIDTH	4

#define SIR1_SPEED_DATARATE_INDEX	4

#define SIR1_SPEED_DATARATE_WIDTH	2

#define SIR1_SPEED_PLLSEL_INDEX		3

#define SIR1_SPEED_PLLSEL_WIDTH		1

#define SIR1_SPEED_RATECHANGE_INDEX	6

#define SIR1_SPEED_RATECHANGE_WIDTH	1

#define SIR1_SPEED_TXAMP_INDEX		8

#define SIR1_SPEED_TXAMP_WIDTH		4

#define SIR1_SPEED_WORDMODE_INDEX	0

#define SIR1_SPEED_WORDMODE_WIDTH	3



/* SerDes RxTx register offsets */

#define RXTX_REG6			0x0018

#define RXTX_REG20			0x0050

#define RXTX_REG22			0x0058

#define RXTX_REG114			0x01c8

#define RXTX_REG129			0x0204



/* SerDes RxTx register entry bit positions and sizes */

#define RXTX_REG6_RESETB_RXD_INDEX	8

#define RXTX_REG6_RESETB_RXD_WIDTH	1

#define RXTX_REG20_BLWC_ENA_INDEX	2

#define RXTX_REG20_BLWC_ENA_WIDTH	1

#define RXTX_REG114_PQ_REG_INDEX	9

#define RXTX_REG114_PQ_REG_WIDTH	7

#define RXTX_REG129_RXDFE_CONFIG_INDEX	14

#define RXTX_REG129_RXDFE_CONFIG_WIDTH	2



/* Descriptor/Packet entry bit positions and sizes */

#define RX_PACKET_ERRORS_CRC_INDEX		2

#define RX_PACKET_ERRORS_CRC_WIDTH		1
@@ -973,10 +1015,47 @@ 
#define TX_NORMAL_DESC2_VLAN_INSERT		0x2



/* MDIO undefined or vendor specific registers */

#ifndef MDIO_PMA_10GBR_PMD_CTRL

#define MDIO_PMA_10GBR_PMD_CTRL		0x0096

#endif



#ifndef MDIO_PMA_10GBR_FECCTRL

#define MDIO_PMA_10GBR_FECCTRL		0x00ab

#endif



#ifndef MDIO_AN_XNP

#define MDIO_AN_XNP			0x0016

#endif



#ifndef MDIO_AN_LPX

#define MDIO_AN_LPX			0x0019

#endif



#ifndef MDIO_AN_COMP_STAT

#define MDIO_AN_COMP_STAT		0x0030

#endif



#ifndef MDIO_AN_INTMASK

#define MDIO_AN_INTMASK			0x8001

#endif



#ifndef MDIO_AN_INT

#define MDIO_AN_INT			0x8002

#endif



#ifndef MDIO_CTRL1_SPEED1G

#define MDIO_CTRL1_SPEED1G		(MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)

#endif



/* MDIO mask values */

#define XGBE_XNP_MCF_NULL_MESSAGE	0x001

#define XGBE_XNP_ACK_PROCESSED		BIT(12)

#define XGBE_XNP_MP_FORMATTED		BIT(13)

#define XGBE_XNP_NP_EXCHANGE		BIT(15)



#define XGBE_KR_TRAINING_START		BIT(0)

#define XGBE_KR_TRAINING_ENABLE		BIT(1)



/* Bit setting and getting macros

 *  The get macro will extract the current bit field value from within

 *  the variable
@@ -1118,6 +1197,82 @@ do { \ 
#define XPCS_IOREAD(_pdata, _off)					\

	ioread32((_pdata)->xpcs_regs + (_off))



/* Macros for building, reading or writing register values or bits

 * within the register values of SerDes integration registers.

 */

#define XSIR_GET_BITS(_var, _prefix, _field)                            \

	GET_BITS((_var),                                                \

		 _prefix##_##_field##_INDEX,                            \

		 _prefix##_##_field##_WIDTH)



#define XSIR_SET_BITS(_var, _prefix, _field, _val)                      \

	SET_BITS((_var),                                                \

		 _prefix##_##_field##_INDEX,                            \

		 _prefix##_##_field##_WIDTH, (_val))



#define XSIR0_IOREAD(_pdata, _reg)					\

	ioread16((_pdata)->sir0_regs + _reg)



#define XSIR0_IOREAD_BITS(_pdata, _reg, _field)				\

	GET_BITS(XSIR0_IOREAD((_pdata), _reg),				\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH)



#define XSIR0_IOWRITE(_pdata, _reg, _val)				\

	iowrite16((_val), (_pdata)->sir0_regs + _reg)



#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val)			\

do {									\

	u16 reg_val = XSIR0_IOREAD((_pdata), _reg);			\

	SET_BITS(reg_val,						\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH, (_val));			\

	XSIR0_IOWRITE((_pdata), _reg, reg_val);				\

} while (0)



#define XSIR1_IOREAD(_pdata, _reg)					\

	ioread16((_pdata)->sir1_regs + _reg)



#define XSIR1_IOREAD_BITS(_pdata, _reg, _field)				\

	GET_BITS(XSIR1_IOREAD((_pdata), _reg),				\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH)



#define XSIR1_IOWRITE(_pdata, _reg, _val)				\

	iowrite16((_val), (_pdata)->sir1_regs + _reg)



#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val)			\

do {									\

	u16 reg_val = XSIR1_IOREAD((_pdata), _reg);			\

	SET_BITS(reg_val,						\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH, (_val));			\

	XSIR1_IOWRITE((_pdata), _reg, reg_val);				\

} while (0)



/* Macros for building, reading or writing register values or bits

 * within the register values of SerDes RxTx registers.

 */

#define XRXTX_IOREAD(_pdata, _reg)					\

	ioread16((_pdata)->rxtx_regs + _reg)



#define XRXTX_IOREAD_BITS(_pdata, _reg, _field)				\

	GET_BITS(XRXTX_IOREAD((_pdata), _reg),				\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH)



#define XRXTX_IOWRITE(_pdata, _reg, _val)				\

	iowrite16((_val), (_pdata)->rxtx_regs + _reg)



#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val)			\

do {									\

	u16 reg_val = XRXTX_IOREAD((_pdata), _reg);			\

	SET_BITS(reg_val,						\

		 _reg##_##_field##_INDEX,				\

		 _reg##_##_field##_WIDTH, (_val));			\

	XRXTX_IOWRITE((_pdata), _reg, reg_val);				\

} while (0)



/* Macros for building, reading or writing register values or bits

 * using MDIO.  Different from above because of the use of standardized

 * Linux include values.  No shifting is performed with the bit