Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7bcbad01 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: clk-alpha-pll: Add support for Regera PLL 



Regera PLL ops are required to control the PLL from HLOS clock driver,
thus add support for the same.

Change-Id: Ie0f5107de6b016ffe8e24f7be70cf4eee7eba55a
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent fb511cfd

drivers/clk/qcom/clk-alpha-pll.c

+271 −1
Original line number Diff line number Diff line
@@ -178,6 +178,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_OPMODE] = 0x28,

		[PLL_OFF_STATUS] = 0x38,

	},

	[CLK_ALPHA_PLL_TYPE_REGERA] =  {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_ALPHA_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,

		[PLL_OFF_CONFIG_CTL] = 0x10,

		[PLL_OFF_CONFIG_CTL_U] = 0x14,

		[PLL_OFF_CONFIG_CTL_U1] = 0x18,

		[PLL_OFF_TEST_CTL] = 0x1c,

		[PLL_OFF_TEST_CTL_U] = 0x20,

		[PLL_OFF_TEST_CTL_U1] = 0x24,

		[PLL_OFF_OPMODE] = 0x28,

		[PLL_OFF_STATUS] = 0x38,

	},

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -3145,3 +3158,260 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 
	.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,

};

EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);



int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config)

{

	u32 mode_regval;

	int ret;



	if (!config) {

		pr_err("PLL configuration missing.\n");

		return -EINVAL;

	}



	ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);

	if (ret)

		return ret;



	if (mode_regval & PLL_LOCK_DET) {

		pr_warn("PLL is already enabled. Skipping configuration.\n");

		return 0;

	}



	if (config->alpha)

		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);



	if (config->l)

		regmap_write(regmap, PLL_L_VAL(pll), config->l);



	if (config->config_ctl_val)

		regmap_write(regmap, PLL_CONFIG_CTL(pll),

						config->config_ctl_val);



	if (config->config_ctl_hi_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

						config->config_ctl_hi_val);



	if (config->config_ctl_hi1_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),

						config->config_ctl_hi1_val);



	if (config->user_ctl_val)

		regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);



	if (config->test_ctl_val)

		regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);



	if (config->test_ctl_hi_val)

		regmap_write(regmap, PLL_TEST_CTL_U(pll),

						config->test_ctl_hi_val);



	if (config->test_ctl_hi1_val)

		regmap_write(regmap, PLL_TEST_CTL_U1(pll),

						config->test_ctl_hi1_val);



	/* Set operation mode to OFF */

	regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);



	return 0;

}



static int clk_regera_pll_enable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, l_val;

	int ret;



	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);

	if (ret)

		return ret;



	/* If in FSM mode, just vote for it */

	if (val & PLL_VOTE_FSM_ENA) {

		ret = clk_enable_regmap(hw);

		if (ret)

			return ret;

		return wait_for_pll_enable_active(pll);

	}



	ret = regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l_val);

	if (ret)

		return ret;



	/* PLL has lost it's L value, needs reconfiguration */

	if (!l_val) {

		ret = clk_regera_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	/* Get the PLL out of bypass mode */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

						PLL_BYPASSNL, PLL_BYPASSNL);

	if (ret)

		return ret;



	/*

	 * H/W requires a 1us delay between disabling the bypass and

	 * de-asserting the reset.

	 */

	mb();

	udelay(1);



	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

						 PLL_RESET_N, PLL_RESET_N);

	if (ret)

		return ret;



	/* Set operation mode to RUN */

	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_OPMODE_RUN);



	ret = wait_for_pll_enable_lock(pll);

	if (ret)

		return ret;



	/* Enable the PLL outputs */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),

				ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);

	if (ret)

		return ret;



	/* Enable the global PLL outputs */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

				 PLL_OUTCTRL, PLL_OUTCTRL);

	if (ret)

		return ret;



	/* Ensure that the write above goes through before returning. */

	mb();

	return ret;

}



static void clk_regera_pll_disable(struct clk_hw *hw)

{

	int ret;

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, mask;



	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);

	if (ret)

		return;



	/* If in FSM mode, just unvote it */

	if (val & PLL_VOTE_FSM_ENA) {

		clk_disable_regmap(hw);

		return;

	}



	/* Disable the global PLL output */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

							PLL_OUTCTRL, 0);

	if (ret)

		return;



	/* Disable the PLL outputs */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),

					ZONDA_PLL_OUT_MASK, 0);



	/* Put the PLL in bypass and reset */

	mask = PLL_RESET_N | PLL_BYPASSNL;

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);

	if (ret)

		return;



	/* Place the PLL mode in OFF state */

	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);

}



static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate,

				  unsigned long prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;

	u32 l, regval, alpha_width = pll_alpha_width(pll);

	u64 a;

	int ret;



	ret = regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);

	if (ret)

		return ret;



	/* PLL has lost it's L value, needs reconfiguration */

	if (!l) {

		ret = clk_regera_pll_configure(pll, pll->clkr.regmap,

						pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);

	/*

	 * Due to a limited number of bits for fractional rate programming, the

	 * rounded up rate could be marginally higher than the requested rate.

	 */

	if (rrate > (rate + PLL_OUT_RATE_MARGIN) || rrate < rate) {

		pr_err("Call set rate on the PLL with rounded rates!\n");

		return -EINVAL;

	}



	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);

	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);



	/* Return early if the PLL is disabled */

	ret = regmap_read(pll->clkr.regmap, PLL_OPMODE(pll), &regval);

	if (ret)

		return ret;



	if (regval == PLL_OPMODE_STANDBY)

		return 0;



	/* Wait before polling for the frequency latch */

	udelay(5);



	ret = wait_for_pll_enable_lock(pll);

	if (ret)

		return ret;



	/* Wait for PLL output to stabilize */

	udelay(100);

	return 0;

}



static unsigned long

clk_regera_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 l, frac, alpha_width = pll_alpha_width(pll);



	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);

	regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);



	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);

}



const struct clk_ops clk_regera_pll_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,

	.pre_rate_change = clk_pre_change_regmap,

	.post_rate_change = clk_post_change_regmap,

	.enable = clk_regera_pll_enable,

	.disable = clk_regera_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_regera_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_regera_pll_set_rate,

#ifdef CONFIG_COMMON_CLK_QCOM_DEBUG

	.list_rate_vdd_level = clk_list_rate_vdd_level,

#endif

};

EXPORT_SYMBOL_GPL(clk_regera_pll_ops);

drivers/clk/qcom/clk-alpha-pll.h

+5 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_ZONDA,

	CLK_ALPHA_PLL_TYPE_LUCID_5LPE,

	CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,

	CLK_ALPHA_PLL_TYPE_REGERA,

	CLK_ALPHA_PLL_TYPE_MAX,

};
@@ -153,6 +154,8 @@ extern const struct clk_ops clk_trion_fixed_pll_ops; 
extern const struct clk_ops clk_trion_pll_postdiv_ops;

extern const struct clk_ops clk_trion_pll_ops;



extern const struct clk_ops clk_regera_pll_ops;



void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);

int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -169,4 +172,6 @@ int clk_zonda_5lpe_pll_configure(struct clk_alpha_pll *pll, 
				const struct alpha_pll_config *config);

int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

#endif