Loading drivers/gpu/msm/kgsl_iommu.c +11 −15 Original line number Diff line number Diff line Loading @@ -841,8 +841,7 @@ static void kgsl_iommu_disable_clk(struct kgsl_mmu *mmu) */ WARN_ON(atomic_read(&iommu->clk_enable_count) < 0); for (j = (KGSL_IOMMU_MAX_CLKS - 1); j >= 0; j--) if (iommu->clks[j]) for (j = 0; j < iommu->num_clks; j++) clk_disable_unprepare(iommu->clks[j]); if (!IS_ERR_OR_NULL(iommu->cx_gdsc)) Loading Loading @@ -877,10 +876,9 @@ static void kgsl_iommu_enable_clk(struct kgsl_mmu *mmu) if (!IS_ERR_OR_NULL(iommu->cx_gdsc)) WARN_ON(regulator_enable(iommu->cx_gdsc)); for (j = 0; j < KGSL_IOMMU_MAX_CLKS; j++) { if (iommu->clks[j]) for (j = 0; j < iommu->num_clks; j++) kgsl_iommu_clk_prepare_enable(iommu->clks[j]); } atomic_inc(&iommu->clk_enable_count); } Loading Loading @@ -2606,7 +2604,7 @@ static struct kgsl_mmu_ops kgsl_iommu_ops; int kgsl_iommu_probe(struct kgsl_device *device) { u32 val[2]; int ret, i, index = 0; int ret, i; struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device); struct platform_device *pdev; struct kgsl_mmu *mmu = &device->mmu; Loading Loading @@ -2640,6 +2638,10 @@ int kgsl_iommu_probe(struct kgsl_device *device) pdev = of_find_device_by_node(node); iommu->pdev = pdev; iommu->num_clks = 0; iommu->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(kgsl_iommu_clocks), sizeof(struct clk **), GFP_KERNEL); /* Get the clock from the KGSL device */ for (i = 0; i < ARRAY_SIZE(kgsl_iommu_clocks); i++) { Loading @@ -2662,13 +2664,7 @@ int kgsl_iommu_probe(struct kgsl_device *device) if (IS_ERR(c)) continue; if (index >= KGSL_IOMMU_MAX_CLKS) { dev_err(device->dev, "dt: too many clocks defined\n"); platform_device_put(pdev); goto err; } iommu->clks[index++] = c; iommu->clks[iommu->num_clks++] = c; } /* Get the CX regulator if it is available */ Loading drivers/gpu/msm/kgsl_iommu.h +2 −4 Original line number Diff line number Diff line Loading @@ -69,9 +69,6 @@ /* FSR fields */ #define KGSL_IOMMU_FSR_SS_SHIFT 30 /* Max number of iommu clks per IOMMU unit */ #define KGSL_IOMMU_MAX_CLKS 7 /* offset at which a nop command is placed in setstate */ #define KGSL_IOMMU_SETSTATE_NOP_OFFSET 1024 Loading Loading @@ -118,7 +115,8 @@ struct kgsl_iommu { void __iomem *regbase; struct kgsl_memdesc *setstate; atomic_t clk_enable_count; struct clk *clks[KGSL_IOMMU_MAX_CLKS]; struct clk **clks; int num_clks; struct kgsl_memdesc *smmu_info; /** @pdev: Pointer to the platform device for the IOMMU device */ struct platform_device *pdev; Loading Loading
drivers/gpu/msm/kgsl_iommu.c +11 −15 Original line number Diff line number Diff line Loading @@ -841,8 +841,7 @@ static void kgsl_iommu_disable_clk(struct kgsl_mmu *mmu) */ WARN_ON(atomic_read(&iommu->clk_enable_count) < 0); for (j = (KGSL_IOMMU_MAX_CLKS - 1); j >= 0; j--) if (iommu->clks[j]) for (j = 0; j < iommu->num_clks; j++) clk_disable_unprepare(iommu->clks[j]); if (!IS_ERR_OR_NULL(iommu->cx_gdsc)) Loading Loading @@ -877,10 +876,9 @@ static void kgsl_iommu_enable_clk(struct kgsl_mmu *mmu) if (!IS_ERR_OR_NULL(iommu->cx_gdsc)) WARN_ON(regulator_enable(iommu->cx_gdsc)); for (j = 0; j < KGSL_IOMMU_MAX_CLKS; j++) { if (iommu->clks[j]) for (j = 0; j < iommu->num_clks; j++) kgsl_iommu_clk_prepare_enable(iommu->clks[j]); } atomic_inc(&iommu->clk_enable_count); } Loading Loading @@ -2606,7 +2604,7 @@ static struct kgsl_mmu_ops kgsl_iommu_ops; int kgsl_iommu_probe(struct kgsl_device *device) { u32 val[2]; int ret, i, index = 0; int ret, i; struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device); struct platform_device *pdev; struct kgsl_mmu *mmu = &device->mmu; Loading Loading @@ -2640,6 +2638,10 @@ int kgsl_iommu_probe(struct kgsl_device *device) pdev = of_find_device_by_node(node); iommu->pdev = pdev; iommu->num_clks = 0; iommu->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(kgsl_iommu_clocks), sizeof(struct clk **), GFP_KERNEL); /* Get the clock from the KGSL device */ for (i = 0; i < ARRAY_SIZE(kgsl_iommu_clocks); i++) { Loading @@ -2662,13 +2664,7 @@ int kgsl_iommu_probe(struct kgsl_device *device) if (IS_ERR(c)) continue; if (index >= KGSL_IOMMU_MAX_CLKS) { dev_err(device->dev, "dt: too many clocks defined\n"); platform_device_put(pdev); goto err; } iommu->clks[index++] = c; iommu->clks[iommu->num_clks++] = c; } /* Get the CX regulator if it is available */ Loading
drivers/gpu/msm/kgsl_iommu.h +2 −4 Original line number Diff line number Diff line Loading @@ -69,9 +69,6 @@ /* FSR fields */ #define KGSL_IOMMU_FSR_SS_SHIFT 30 /* Max number of iommu clks per IOMMU unit */ #define KGSL_IOMMU_MAX_CLKS 7 /* offset at which a nop command is placed in setstate */ #define KGSL_IOMMU_SETSTATE_NOP_OFFSET 1024 Loading Loading @@ -118,7 +115,8 @@ struct kgsl_iommu { void __iomem *regbase; struct kgsl_memdesc *setstate; atomic_t clk_enable_count; struct clk *clks[KGSL_IOMMU_MAX_CLKS]; struct clk **clks; int num_clks; struct kgsl_memdesc *smmu_info; /** @pdev: Pointer to the platform device for the IOMMU device */ struct platform_device *pdev; Loading