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Commit 7a7f8082 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable device nodes for PIL on SM6150"

parents f0f73a3c 876d50d7

qcom/msm-arm-smmu-sm6150.dtsi

0 → 100644
+249 −0
Original line number Diff line number Diff line 
#include <dt-bindings/interrupt-controller/arm-gic.h>



&soc {

	kgsl_smmu: kgsl-smmu@0x50a0000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x50a0000 0x10000>,

			<0x50c2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,dynamic;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,disable-atos;

		#global-interrupts = <1>;

		qcom,regulator-names = "vdd";

		vdd-supply = <&gpu_cx_gdsc>;

		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

			 <&gpucc GPU_CC_AHB_CLK>,

			 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

		clock-names = "gcc_gpu_memnoc_gfx_clk",

			      "gcc_gpu_snoc_dvm_gfx_clk",

			      "gpu_cc_ahb_clk",

			      "gpu_cc_hlos1_vote_gpu_smmu_clk";

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;



		gfx_0_tbu: gfx_0_tbu@0x50c5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x50c5000 0x1000>,

				<0x50c2200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};



		gfx_1_tbu: gfx_1_tbu@0x50c9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x50c9000 0x1000>,

				<0x50c2208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

		};

	};



	apps_smmu: apps-smmu@0x15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x80000>,

			<0x150c2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,disable-atos;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;



		interconnects = <&system_noc MASTER_GEM_NOC_SNOC

				&config_noc SLAVE_IMEM_CFG>;

		qcom,active-only;



		anoc_1_tbu: anoc_1_tbu@0x150c5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150c5000 0x1000>,

				<0x150c2200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;

			qcom,active-only;

			interconnects = <&system_noc MASTER_GEM_NOC_SNOC

					&config_noc SLAVE_IMEM_CFG>;

		};



		anoc_2_tbu: anoc_2_tbu@0x150c9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150c9000 0x1000>,

				<0x150c2208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;

			qcom,active-only;

			interconnects = <&system_noc MASTER_GEM_NOC_SNOC

					&config_noc SLAVE_IMEM_CFG>;

		};



		mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150cd000 0x1000>,

				<0x150c2210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;

			qcom,active-only;

			interconnects = <&mmss_noc MASTER_MDP0

					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;

		};



		mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150d1000 0x1000>,

				<0x150c2218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;

			qcom,active-only;

			interconnects = <&mmss_noc MASTER_CAMNOC_SF

					&mmss_noc SLAVE_MNOC_SF_MEM_NOC>;

		};



		compute_dsp_tbu: compute_dsp_tbu@0x150d5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150d5000 0x1000>,

				<0x150c2220 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1000 0x400>;

			/* No GDSC */

			qcom,active-only;

			interconnects = <&system_noc MASTER_GEM_NOC_SNOC

					&config_noc SLAVE_IMEM_CFG>;

		};



		adsp_tbu: adsp_tbu@0x150d9000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x150d9000 0x1000>,

				<0x150c2228 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x1400 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;

			qcom,active-only;

			interconnects = <&system_noc MASTER_GEM_NOC_SNOC

					&config_noc SLAVE_IMEM_CFG>;

		};

	};



	kgsl_iommu_test_device {

		compatible = "iommu-debug-test";

		iommus = <&kgsl_smmu 0x7 0>;

	};



	kgsl_iommu_coherent_test_device {

		compatible = "iommu-debug-test";

		iommus = <&kgsl_smmu 0x9 0>;

		dma-coherent;

	};



	apps_iommu_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x21 0>;

	};



	apps_iommu_coherent_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x23 0>;

		dma-coherent;

	};

};



&kgsl_smmu {

	qcom,actlr =

		/* All CBs of GFX: +15 deep PF */

		<0x0 0x7ff 0x303>;

};



&apps_smmu {

	qcom,actlr =

		/* HF and SF TBUs: +3 deep PF */

		<0x800 0x7ff 0x103>;

};

qcom/sa6155-adp-common.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -3,3 +3,17 @@ 
&qupv3_0 {

	status = "ok";

};



&soc {

	qcom,lpass@62400000 {

	status = "ok";

	};



	qcom,venus@aae0000 {

	status = "ok";

	};



	qcom,turing@8300000 {

	status = "ok";

	};

};

qcom/sa6155-pmic.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -39,5 +39,11 @@ 
	/delete-node/ rpmh-regulator-bobc1;

};



&soc {

		qcom,lpass@62400000 {

			vdd_cx-supply = <&VDD_CX_LEVEL>;

		};

};



#include "sa6155-regulator.dtsi"

#include "pm6155.dtsi"

qcom/sm6150.dtsi

+113 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <dt-bindings/interconnect/qcom,osm-l3.h>

#include <dt-bindings/interconnect/qcom,sm6150.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>



/ {

	model = "Qualcomm Technologies, Inc. SM6150";
@@ -1560,6 +1561,116 @@ 
			#interrupt-cells = <2>;

		};

	};



	qcom,lpass@62400000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x62400000 0x00100>;



		vdd_cx-supply = <&L8A_LEVEL>;

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;

		qcom,proxy-reg-names = "vdd_cx";



		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "xo";

		qcom,proxy-clock-names = "xo";



		qcom,pas-id = <1>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <423>;

		qcom,sysmon-id = <1>;

		qcom,ssctl-instance-id = <0x14>;

		qcom,firmware-name = "adsp";

		memory-region = <&pil_adsp_mem>;

		qcom,signal-aop;

		qcom,complete-ramdump;



		/* Inputs from lpass */

		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

						<&adsp_smp2p_in 0 0>,

						<&adsp_smp2p_in 2 0>,

						<&adsp_smp2p_in 1 0>,

						<&adsp_smp2p_in 3 0>,

						<&adsp_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",

						"qcom,err-fatal",

						"qcom,proxy-unvote",

						"qcom,err-ready",

						"qcom,stop-ack",

						"qcom,shutdown-ack";



		/* Outputs to lpass */

		qcom,smem-states = <&adsp_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";



		mboxes = <&qmp_aop 0>;

		mbox-names = "adsp-pil";

	};

	qcom,turing@8300000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0x8300000 0x100000>;



		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names = "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;



		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "xo";

		qcom,proxy-clock-names = "xo";



		qcom,pas-id = <18>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,smem-id = <601>;

		qcom,sysmon-id = <7>;

		qcom,ssctl-instance-id = <0x17>;

		qcom,firmware-name = "cdsp";

		memory-region = <&pil_cdsp_mem>;

		qcom,signal-aop;

		qcom,complete-ramdump;



		/* Inputs from turing */

		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,

						<&cdsp_smp2p_in 0 0>,

						<&cdsp_smp2p_in 2 0>,

						<&cdsp_smp2p_in 1 0>,

						<&cdsp_smp2p_in 3 0>,

						<&cdsp_smp2p_in 7 0>;



		interrupt-names = "qcom,wdog",

						"qcom,err-fatal",

						"qcom,proxy-unvote",

						"qcom,err-ready",

						"qcom,stop-ack",

						"qcom,shutdown-ack";



		/* Outputs to turing */

		qcom,smem-states = <&cdsp_smp2p_out 0>;

		qcom,smem-state-names = "qcom,force-stop";



		mboxes = <&qmp_aop 0>;

		mbox-names = "cdsp-pil";

	};



	qcom,venus@aae0000 {

		compatible = "qcom,pil-tz-generic";

		reg = <0xaae0000 0x4000>;



		vdd-supply = <&venus_gdsc>;

		qcom,proxy-reg-names = "vdd";



		clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,

				<&videocc VIDEO_CC_VENUS_AHB_CLK>,

				<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;

		clock-names = "core_clk", "iface_clk", "bus_clk";

		qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";



		qcom,pas-id = <9>;

		interconnect-names  = "pil-venus";

		interconnects = <&mmss_noc MASTER_VIDEO_P0

				&mc_virt SLAVE_EBI1>;

		qcom,proxy-timeout-ms = <100>;

		qcom,firmware-name = "venus";

		memory-region = <&pil_video_mem>;

	};

};



#include "sm6150-qupv3.dtsi"
@@ -1663,3 +1774,5 @@ 
&venus_gdsc {

	status = "ok";

};



#include "msm-arm-smmu-sm6150.dtsi"