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Commit 7a74a443 authored by Stephen Warren's avatar Stephen Warren
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ARM: tegra: fix overflow in tegra20_pll_clk_round_rate() 



32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000.
Use 64-bit math to prevent this.

Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent fa67ccb6

arch/arm/mach-tegra/tegra20_clocks.c

+1 −1
Original line number Diff line number Diff line
@@ -789,7 +789,7 @@ static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate, 
	struct clk_tegra *c = to_clk_tegra(hw);

	const struct clk_pll_freq_table *sel;

	unsigned long input_rate = *prate;

	unsigned long output_rate = *prate;

	u64 output_rate = *prate;

	int mul;

	int div;