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Commit 7a67e11d authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
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r8169: simplify RTL8169 PHY initialization 



PCI_LATENCY_TIMER is ignored on PCIe, therefore we have to do this
for the PCI chips (version <= 06) only. Also we can move setting
PCI_CACHE_LINE_SIZE.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c8c618af

drivers/net/ethernet/realtek/r8169.c

+2 −5
Original line number Diff line number Diff line
@@ -4048,16 +4048,13 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 
	rtl_hw_phy_config(dev);



	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {

		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);

		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);

		netif_dbg(tp, drv, dev,

			  "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");

		RTL_W8(tp, 0x82, 0x01);

	}



	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);



	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)

		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);



	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {

		netif_dbg(tp, drv, dev,

			  "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");