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Commit 7a31f6f4 authored by Hiroshi DOYU's avatar Hiroshi DOYU Committed by Joerg Roedel
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ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver 



Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit). This patch
implements struct iommu_ops for SMMU for the upper IOMMU API.

This H/W module supports multiple virtual address spaces(domain x4),
and manages 2 level H/W translation pagetable.

Signed-off-by: default avatarHiroshi DOYU <hdoyu@nvidia.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent d53e54b4

arch/arm/mach-tegra/include/mach/smmu.h

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+63 −0
Original line number Diff line number Diff line 
/*

 * IOMMU API for SMMU in Tegra30

 *

 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program; if not, write to the Free Software Foundation, Inc.,

 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

 */



#ifndef	MACH_SMMU_H

#define	MACH_SMMU_H



enum smmu_hwgrp {

	HWGRP_AFI,

	HWGRP_AVPC,

	HWGRP_DC,

	HWGRP_DCB,

	HWGRP_EPP,

	HWGRP_G2,

	HWGRP_HC,

	HWGRP_HDA,

	HWGRP_ISP,

	HWGRP_MPE,

	HWGRP_NV,

	HWGRP_NV2,

	HWGRP_PPCS,

	HWGRP_SATA,

	HWGRP_VDE,

	HWGRP_VI,



	HWGRP_COUNT,



	HWGRP_END = ~0,

};



#define HWG_AFI		(1 << HWGRP_AFI)

#define HWG_AVPC	(1 << HWGRP_AVPC)

#define HWG_DC		(1 << HWGRP_DC)

#define HWG_DCB		(1 << HWGRP_DCB)

#define HWG_EPP		(1 << HWGRP_EPP)

#define HWG_G2		(1 << HWGRP_G2)

#define HWG_HC		(1 << HWGRP_HC)

#define HWG_HDA		(1 << HWGRP_HDA)

#define HWG_ISP		(1 << HWGRP_ISP)

#define HWG_MPE		(1 << HWGRP_MPE)

#define HWG_NV		(1 << HWGRP_NV)

#define HWG_NV2		(1 << HWGRP_NV2)

#define HWG_PPCS	(1 << HWGRP_PPCS)

#define HWG_SATA	(1 << HWGRP_SATA)

#define HWG_VDE		(1 << HWGRP_VDE)

#define HWG_VI		(1 << HWGRP_VI)



#endif	/* MACH_SMMU_H */

drivers/iommu/Kconfig

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@@ -152,4 +152,14 @@ config TEGRA_IOMMU_GART 
	  space through the GART (Graphics Address Relocation Table)

	  hardware included on Tegra SoCs.



config TEGRA_IOMMU_SMMU

	bool "Tegra SMMU IOMMU Support"

	depends on ARCH_TEGRA_3x_SOC

	select IOMMU_API

	help

	  Enables support for remapping discontiguous physical memory

	  shared with the operating system into contiguous I/O virtual

	  space through the SMMU (System Memory Management Unit)

	  hardware included on Tegra SoCs.



endif # IOMMU_SUPPORT

drivers/iommu/Makefile

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@@ -9,3 +9,4 @@ obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o 
obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o

obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o

obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o

obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o

drivers/iommu/tegra-smmu.c

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File added.

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