Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7a234d03 authored by Li Yang's avatar Li Yang Committed by Paul Mackerras
Browse files

[POWERPC] Add MPC8360EMDS default dts file 



Add MPC8360EMDS default device-tree source file

Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarJiang Bo <Tanya.jiang@freescale.com>
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent bc141dea

arch/powerpc/boot/dts/mpc8360emds.dts

0 → 100644
+375 −0
Original line number Diff line number Diff line 
/*

 * MPC8360E EMDS Device Tree Source

 *

 * Copyright 2006 Freescale Semiconductor Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */





/*

/memreserve/	00000000 1000000;

*/



/ {

	model = "MPC8360EPB";

	compatible = "MPC83xx";

	#address-cells = <1>;

	#size-cells = <1>;

	linux,phandle = <100>;



	cpus {

		#cpus = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		linux,phandle = <200>;



		PowerPC,8360@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <20>;	// 32 bytes

			i-cache-line-size = <20>;	// 32 bytes

			d-cache-size = <8000>;		// L1, 32K

			i-cache-size = <8000>;		// L1, 32K

			timebase-frequency = <3EF1480>;

			bus-frequency = <FBC5200>;

			clock-frequency = <1F78A400>;

			32-bit;

			linux,phandle = <201>;

			linux,boot-cpu;

		};

	};



	memory {

		device_type = "memory";

		linux,phandle = <300>;

		reg = <00000000 10000000>;

	};



	bcsr@f8000000 {

		device_type = "board-control";

		reg = <f8000000 8000>;

	};



	soc8360@e0000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		#interrupt-cells = <2>;

		device_type = "soc";

		ranges = <0 e0000000 00100000>;

		reg = <e0000000 00000200>;

		bus-frequency = <FBC5200>;



		wdt@200 {

			device_type = "watchdog";

			compatible = "mpc83xx_wdt";

			reg = <200 100>;

		};



		i2c@3000 {

			device_type = "i2c";

			compatible = "fsl-i2c";

			reg = <3000 100>;

			interrupts = <e 8>;

			interrupt-parent = <700>;

			dfsrr;

		};



		i2c@3100 {

			device_type = "i2c";

			compatible = "fsl-i2c";

			reg = <3100 100>;

			interrupts = <f 8>;

			interrupt-parent = <700>;

			dfsrr;

		};



		serial@4500 {

			device_type = "serial";

			compatible = "ns16550";

			reg = <4500 100>;

			clock-frequency = <FBC5200>;

			interrupts = <9 8>;

			interrupt-parent = <700>;

		};



		serial@4600 {

			device_type = "serial";

			compatible = "ns16550";

			reg = <4600 100>;

			clock-frequency = <FBC5200>;

			interrupts = <a 8>;

			interrupt-parent = <700>;

		};



		crypto@30000 {

			device_type = "crypto";

			model = "SEC2";

			compatible = "talitos";

			reg = <30000 10000>;

			interrupts = <b 8>;

			interrupt-parent = <700>;

			num-channels = <4>;

			channel-fifo-len = <18>;

			exec-units-mask = <0000007e>;

			/* desc mask is for rev1.x, we need runtime fixup for >=2.x */

			descriptor-types-mask = <01010ebf>;

		};



		pci@8500 {

			linux,phandle = <8500>;

			interrupt-map-mask = <f800 0 0 7>;

			interrupt-map = <



					/* IDSEL 0x11 AD17 */

					 8800 0 0 1 700 14 8

					 8800 0 0 2 700 15 8

					 8800 0 0 3 700 16 8

					 8800 0 0 4 700 17 8



					/* IDSEL 0x12 AD18 */

					 9000 0 0 1 700 16 8

					 9000 0 0 2 700 17 8

					 9000 0 0 3 700 14 8

					 9000 0 0 4 700 15 8



					/* IDSEL 0x13 AD19 */

					 9800 0 0 1 700 17 8

					 9800 0 0 2 700 14 8

					 9800 0 0 3 700 15 8

					 9800 0 0 4 700 16 8



					/* IDSEL 0x15 AD21*/

					 a800 0 0 1 700 14 8

					 a800 0 0 2 700 15 8

					 a800 0 0 3 700 16 8

					 a800 0 0 4 700 17 8



					/* IDSEL 0x16 AD22*/

					 b000 0 0 1 700 17 8

					 b000 0 0 2 700 14 8

					 b000 0 0 3 700 15 8

					 b000 0 0 4 700 16 8



					/* IDSEL 0x17 AD23*/

					 b800 0 0 1 700 16 8

					 b800 0 0 2 700 17 8

					 b800 0 0 3 700 14 8

					 b800 0 0 4 700 15 8



					/* IDSEL 0x18 AD24*/

					 c000 0 0 1 700 15 8

					 c000 0 0 2 700 16 8

					 c000 0 0 3 700 17 8

					 c000 0 0 4 700 14 8>;

			interrupt-parent = <700>;

			interrupts = <42 8>;

			bus-range = <0 0>;

			ranges = <02000000 0 a0000000 a0000000 0 10000000

				  42000000 0 80000000 80000000 0 10000000

				  01000000 0 00000000 e2000000 0 00100000>;

			clock-frequency = <3f940aa>;

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = <8500 100>;

			compatible = "83xx";

			device_type = "pci";

		};



		pic@700 {

			linux,phandle = <700>;

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <700 100>;

			built-in;

			device_type = "ipic";

		};



		par_io@1400 {

			reg = <1400 100>;

			device_type = "par_io";

			num-ports = <7>;



			ucc_pin@01 {

				linux,phandle = <140001>;

				pio-map = <

			/* port  pin  dir  open_drain  assignment  has_irq */

					0  3  1  0  1  0 	/* TxD0 */

					0  4  1  0  1  0 	/* TxD1 */

					0  5  1  0  1  0 	/* TxD2 */

					0  6  1  0  1  0 	/* TxD3 */

					1  6  1  0  3  0 	/* TxD4 */

					1  7  1  0  1  0 	/* TxD5 */

					1  9  1  0  2  0 	/* TxD6 */

					1  a  1  0  2  0 	/* TxD7 */

					0  9  2  0  1  0 	/* RxD0 */

					0  a  2  0  1  0 	/* RxD1 */

					0  b  2  0  1  0 	/* RxD2 */

					0  c  2  0  1  0 	/* RxD3 */

					0  d  2  0  1  0 	/* RxD4 */

					1  1  2  0  2  0 	/* RxD5 */

					1  0  2  0  2  0 	/* RxD6 */

					1  4  2  0  2  0 	/* RxD7 */

					0  7  1  0  1  0 	/* TX_EN */

					0  8  1  0  1  0 	/* TX_ER */

					0  f  2  0  1  0 	/* RX_DV */

					0  10 2  0  1  0 	/* RX_ER */

					0  0  2  0  1  0 	/* RX_CLK */

					2  9  1  0  3  0 	/* GTX_CLK - CLK10 */

					2  8  2  0  1  0>;	/* GTX125 - CLK9 */

			};

			ucc_pin@02 {

				linux,phandle = <140002>;

				pio-map = <

			/* port  pin  dir  open_drain  assignment  has_irq */

					0  11 1  0  1  0   /* TxD0 */

					0  12 1  0  1  0   /* TxD1 */

					0  13 1  0  1  0   /* TxD2 */

					0  14 1  0  1  0   /* TxD3 */

					1  2  1  0  1  0   /* TxD4 */

					1  3  1  0  2  0   /* TxD5 */

					1  5  1  0  3  0   /* TxD6 */

					1  8  1  0  3  0   /* TxD7 */

					0  17 2  0  1  0   /* RxD0 */

					0  18 2  0  1  0   /* RxD1 */

					0  19 2  0  1  0   /* RxD2 */

					0  1a 2  0  1  0   /* RxD3 */

					0  1b 2  0  1  0   /* RxD4 */

					1  c  2  0  2  0   /* RxD5 */

					1  d  2  0  3  0   /* RxD6 */

					1  b  2  0  2  0   /* RxD7 */

					0  15 1  0  1  0   /* TX_EN */

					0  16 1  0  1  0   /* TX_ER */

					0  1d 2  0  1  0   /* RX_DV */

					0  1e 2  0  1  0   /* RX_ER */

					0  1f 2  0  1  0   /* RX_CLK */

					2  2  1  0  2  0   /* GTX_CLK - CLK10 */

					2  3  2  0  1  0   /* GTX125 - CLK4 */

					0  1  3  0  2  0   /* MDIO */

					0  2  1  0  1  0>; /* MDC */

			};



		};

	};



	qe@e0100000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "qe";

		model = "QE";

		ranges = <0 e0100000 00100000>;

		reg = <e0100000 480>;

		brg-frequency = <0>;

		bus-frequency = <179A7B00>;



		muram@10000 {

			device_type = "muram";

			ranges = <0 00010000 0000c000>;



			data-only@0{

				reg = <0 c000>;

			};

		};



		spi@4c0 {

			device_type = "spi";

			compatible = "fsl_spi";

			reg = <4c0 40>;

			interrupts = <2>;

			interrupt-parent = <80>;

			mode = "cpu";

		};



		spi@500 {

			device_type = "spi";

			compatible = "fsl_spi";

			reg = <500 40>;

			interrupts = <1>;

			interrupt-parent = <80>;

			mode = "cpu";

		};



		usb@6c0 {

			device_type = "usb";

			compatible = "qe_udc";

			reg = <6c0 40 8B00 100>;

			interrupts = <b>;

			interrupt-parent = <80>;

			mode = "slave";

		};



		ucc@2000 {

			device_type = "network";

			compatible = "ucc_geth";

			model = "UCC";

			device-id = <1>;

			reg = <2000 200>;

			interrupts = <20>;

			interrupt-parent = <80>;

			mac-address = [ 00 04 9f 00 23 23 ];

			rx-clock = <0>;

			tx-clock = <19>;

			phy-handle = <212000>;

			pio-handle = <140001>;

		};



		ucc@3000 {

			device_type = "network";

			compatible = "ucc_geth";

			model = "UCC";

			device-id = <2>;

			reg = <3000 200>;

			interrupts = <21>;

			interrupt-parent = <80>;

			mac-address = [ 00 11 22 33 44 55 ];

			rx-clock = <0>;

			tx-clock = <14>;

			phy-handle = <212001>;

			pio-handle = <140002>;

		};



		mdio@2120 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2120 18>;

			device_type = "mdio";

			compatible = "ucc_geth_phy";



			ethernet-phy@00 {

				linux,phandle = <212000>;

				interrupt-parent = <700>;

				interrupts = <11 2>;

				reg = <0>;

				device_type = "ethernet-phy";

				interface = <6>; //ENET_1000_GMII

			};

			ethernet-phy@01 {

				linux,phandle = <212001>;

				interrupt-parent = <700>;

				interrupts = <12 2>;

				reg = <1>;

				device_type = "ethernet-phy";

				interface = <6>;

			};

		};



		qeic@80 {

			linux,phandle = <80>;

			interrupt-controller;

			device_type = "qeic";

			#address-cells = <0>;

			#interrupt-cells = <1>;

			reg = <80 80>;

			built-in;

			big-endian;

			interrupts = <20 8 21 8>; //high:32 low:33

			interrupt-parent = <700>;

		};



	};

};