cpufreq: qcom: Set the register for GT Limits Management interrupt



Set the GT_IRQ_CLR bit of EPSS_INTR_CLEAR register to generate the EPSS
hardware GT interrupt when LMH throttle occurs.

Change-Id: I1ba6faf1a28f2d8d06c8d91f3046bb064263cb67
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>

parent bf4eaa44

drivers/cpufreq/qcom-cpufreq-hw.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -317,6 +317,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
		}

		c->is_irq_requested = true;
		writel_relaxed(GT_IRQ_STATUS, c->base + offsets[REG_INTR_EN]);
		writel_relaxed(0x0, c->base + offsets[REG_INTR_CLR]);
		c->is_irq_enabled = true;
		c->freq_limit_attr.attr.name = "dcvsh_freq_limit";
		c->freq_limit_attr.show = dcvsh_freq_limit_show;