cpufreq: qcom: Set the register for GT Limits Management interrupt

Set the GT_IRQ_CLR bit of EPSS_INTR_CLEAR register to generate the EPSS
hardware GT interrupt when LMH throttle occurs.

Change-Id: I1ba6faf1a28f2d8d06c8d91f3046bb064263cb67
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>