Commit 79f29bc3 authored Jul 12, 2021 by Veerabhadrarao Badiganti Committed by Gerrit - the friendly Code Review server Jul 27, 2021

msm: ep_pcie: Allow L1 states while switching back to D0 from D3hot



During D3hot, we are explicitly blocking L1 state by setting
REQ_EXIT_L1 bit of PM_CTRL register. If we transitioning back to D0
from D3 (without D3cold), REQ_EXIT_L1 bit won't get cleared. And
L1 would get blocked till next D3cold. Clear this explicitly during
D0 to avoid this scenario.

Change-Id: Ib168dee255f29832600ebca14eea1ac2ea393985
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>

parent 30e5a66d

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -2275,6 +2275,14 @@ static irqreturn_t ep_pcie_handle_dstate_change_irq(int irq, void *data)
		} else if (dstate == 0) {
		dev->l23_ready = false;
		dev->d0_counter++;
		/*
		* When device is trasistion back to D0 from D3hot
		* (without D3cold), REQ_EXIT_L1 bit won't get cleared.
		* And L1 would get blocked till next D3cold.
		* So clear it explicitly during D0.
		*/
		ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(1), 0);

		atomic_set(&dev->host_wake_pending, 0);
		EP_PCIE_DBG(dev,
		"PCIe V%d: No. %ld change to D0 state, clearing wake pending:%d\n",