Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 79c3ba32 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-06-07-1' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "A small bit more lively this week but not majorly so. I'm away in
  Japan next week for family holiday, so I'll be pretty disconnected,
  I've asked Daniel to do fixes for the week while I'm out.

  The nouveau firmware changes are a bit large, but they address a big
  problem where a whole set of boards don't load with the driver, and
  the new firmware fixes that, so I think it's worth trying to land it
  now.

  core:
   - Allow fb changes in async commits (drivers as well)

  udmabuf:
   - Unmap scatterlist when unmapping udmabuf

  nouveau:
   - firmware loading fixes for secboot firmware on new GPU revision.

  komeda:
   - oops, dma mapping and warning fixes

  arm-hdlcd:
   - clock fixes
   - mode validation fix

  i915:
   - Add a missing Icelake workaround
   - GVT - DMA map fault fix and enforcement fixes

  amdgpu:
   - DCE resume fix
   - New raven variation updates"

* tag 'drm-fixes-2019-06-07-1' of git://anongit.freedesktop.org/drm/drm: (33 commits)
  drm/nouveau/secboot/gp10[2467]: support newer FW to fix SEC2 failures on some boards
  drm/nouveau/secboot: enable loading of versioned LS PMU/SEC2 ACR msgqueue FW
  drm/nouveau/secboot: split out FW version-specific LS function pointers
  drm/nouveau/secboot: pass max supported FW version to LS load funcs
  drm/nouveau/core: support versioned firmware loading
  drm/nouveau/core: pass subdev into nvkm_firmware_get, rather than device
  drm/komeda: Potential error pointer dereference
  drm/komeda: remove set but not used variable 'kcrtc'
  drm/amd/amdgpu: add RLC firmware to support raven1 refresh
  drm/amd/powerplay: add set_power_profile_mode for raven1_refresh
  drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2)
  udmabuf: actually unmap the scatterlist
  drm/arm/hdlcd: Allow a bit of clock tolerance
  drm/arm/hdlcd: Actually validate CRTC modes
  drm/arm/mali-dp: Add a loop around the second set CVAL and try 5 times
  drm/komeda: fixing of DMA mapping sg segment warning
  drm: don't block fb changes for async plane updates
  drm/vc4: fix fb references in async update
  drm/msm: fix fb references in async update
  drm/amd: fix fb references in async update
  ...
parents d4425649 671e2ee5

drivers/dma-buf/udmabuf.c

+1 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ static void unmap_udmabuf(struct dma_buf_attachment *at, 
			  struct sg_table *sg,

			  enum dma_data_direction direction)

{

	dma_unmap_sg(at->dev, sg->sgl, sg->nents, direction);

	sg_free_table(sg);

	kfree(sg);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −9
Original line number Diff line number Diff line
@@ -1589,6 +1589,7 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) 
{

	int r = 0;

	int i;

	uint32_t smu_version;



	if (adev->asic_type >= CHIP_VEGA10) {

		for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1614,17 +1615,10 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) 
			}

		}

	}

	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);



	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {

		r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);

		if (r) {

			pr_err("firmware loading failed\n");

	return r;

}

	}



	return 0;

}



/**

 * amdgpu_device_ip_init - run init for hardware IPs

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+15 −0
Original line number Diff line number Diff line
@@ -2490,6 +2490,21 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev) 


}



int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)

{

	int r = -EINVAL;



	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {

		r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);

		if (r) {

			pr_err("smu firmware loading failed\n");

			return r;

		}

		*smu_version = adev->pm.fw_version;

	}

	return r;

}



int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)

{

	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 
int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);

void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);

void amdgpu_pm_print_power_states(struct amdgpu_device *adev);

int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);

void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);

void amdgpu_dpm_thermal_work_handler(struct work_struct *work);

void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

+3 −1
Original line number Diff line number Diff line
@@ -1072,7 +1072,7 @@ void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 
int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t rptr = amdgpu_ring_get_rptr(ring);

	uint32_t rptr;

	unsigned i;

	int r, timeout = adev->usec_timeout;
@@ -1084,6 +1084,8 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) 
	if (r)

		return r;



	rptr = amdgpu_ring_get_rptr(ring);



	amdgpu_ring_write(ring, VCE_CMD_END);

	amdgpu_ring_commit(ring);