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Commit 7946328f authored by Martyn Welch's avatar Martyn Welch Committed by Greg Kroah-Hartman
Browse files

Staging: vme: Correct checkpatch errors 



Correct numerous checkpatch errors in the vme driver.

Signed-off-by: default avatarMartyn Welch <martyn.welch@ge.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 48d9356e

drivers/staging/vme/bridges/vme_ca91cx42.c

+4 −5
Original line number Diff line number Diff line
@@ -26,9 +26,9 @@ 
#include <linux/spinlock.h>

#include <linux/sched.h>

#include <linux/slab.h>

#include <asm/time.h>

#include <asm/io.h>

#include <asm/uaccess.h>

#include <linux/time.h>

#include <linux/io.h>

#include <linux/uaccess.h>



#include "../vme.h"

#include "../vme_bridge.h"
@@ -1684,9 +1684,8 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	dev_info(&pdev->dev, "Slot ID is %d\n",

		ca91cx42_slot_get(ca91cx42_bridge));



	if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) {

	if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))

		dev_err(&pdev->dev, "CR/CSR configuration failed.\n");

	}



	/* Need to save ca91cx42_bridge pointer locally in link list for use in

	 * ca91cx42_remove()

drivers/staging/vme/bridges/vme_tsi148.c

+82 −104
Original line number Diff line number Diff line
@@ -26,9 +26,9 @@ 
#include <linux/spinlock.h>

#include <linux/sched.h>

#include <linux/slab.h>

#include <asm/time.h>

#include <asm/io.h>

#include <asm/uaccess.h>

#include <linux/time.h>

#include <linux/io.h>

#include <linux/uaccess.h>



#include "../vme.h"

#include "../vme_bridge.h"
@@ -40,27 +40,6 @@ static void tsi148_remove(struct pci_dev *); 
static void __exit tsi148_exit(void);





int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,

	unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);

int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,

	unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);



int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,

        unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);

int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,

	unsigned long long, vme_address_t, vme_cycle_t,	vme_width_t);

ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,

	loff_t);

ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,

	loff_t);

unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,

	unsigned int, unsigned int, loff_t);

int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,

	struct vme_dma_attr *, size_t);

int tsi148_dma_list_exec(struct vme_dma_list *);

int tsi148_dma_list_empty(struct vme_dma_list *);

int tsi148_generate_irq(int, int);



/* Module parameter */

static int err_chk;

static int geoid;
@@ -208,8 +187,7 @@ static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) 
			"Occurred\n");

	}



	error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),

		GFP_ATOMIC);

	error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);

	if (error) {

		error->address = error_addr;

		error->attributes = error_attrib;
@@ -251,10 +229,9 @@ static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, 
	for (i = 7; i > 0; i--) {

		if (stat & (1 << i)) {

			/*

			 * 	Note:   Even though the registers are defined

			 * 	as 32-bits in the spec, we only want to issue

			 * 	8-bit IACK cycles on the bus, read from offset

			 * 	3.

			 * Note: Even though the registers are defined as

			 * 32-bits in the spec, we only want to issue 8-bit

			 * IACK cycles on the bus, read from offset 3.

			 */

			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
@@ -288,9 +265,8 @@ static irqreturn_t tsi148_irqhandler(int irq, void *ptr) 
	/* Only look at unmasked interrupts */

	stat &= enable;



	if (unlikely(!stat)) {

	if (unlikely(!stat))

		return IRQ_NONE;

	}



	/* Call subhandlers as appropriate */

	/* DMA irqs */
@@ -522,7 +498,9 @@ static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge, 
	/* Iterate through errors */

	list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {

		vme_err = list_entry(err_pos, struct vme_bus_error, list);

		if((vme_err->address >= address) && (vme_err->address < bound)){

		if ((vme_err->address >= address) &&

			(vme_err->address < bound)) {



			valid = vme_err;

			break;

		}
@@ -555,7 +533,9 @@ static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge, 
	list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {

		vme_err = list_entry(err_pos, struct vme_bus_error, list);



		if((vme_err->address >= address) && (vme_err->address < bound)){

		if ((vme_err->address >= address) &&

			(vme_err->address < bound)) {



			list_del(err_pos);

			kfree(vme_err);

		}
@@ -844,9 +824,8 @@ static int tsi148_alloc_resource(struct vme_master_resource *image, 
	}



	/* Exit here if size is zero */

	if (size == 0) {

	if (size == 0)

		return 0;

	}



	if (image->bus_resource.name == NULL) {

		image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
@@ -1456,21 +1435,21 @@ static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr, 
	}



	/* Setup cycle types */

	if (cycle & VME_SCT) {

	if (cycle & VME_SCT)

		*attr |= TSI148_LCSR_DSAT_TM_SCT;

	}

	if (cycle & VME_BLT) {



	if (cycle & VME_BLT)

		*attr |= TSI148_LCSR_DSAT_TM_BLT;

	}

	if (cycle & VME_MBLT) {



	if (cycle & VME_MBLT)

		*attr |= TSI148_LCSR_DSAT_TM_MBLT;

	}

	if (cycle & VME_2eVME) {



	if (cycle & VME_2eVME)

		*attr |= TSI148_LCSR_DSAT_TM_2eVME;

	}

	if (cycle & VME_2eSST) {



	if (cycle & VME_2eSST)

		*attr |= TSI148_LCSR_DSAT_TM_2eSST;

	}



	if (cycle & VME_2eSSTB) {

		dev_err(dev, "Currently not setting Broadcast Select "

			"Registers\n");
@@ -1550,21 +1529,21 @@ static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr, 
	}



	/* Setup cycle types */

	if (cycle & VME_SCT) {

	if (cycle & VME_SCT)

		*attr |= TSI148_LCSR_DDAT_TM_SCT;

	}

	if (cycle & VME_BLT) {



	if (cycle & VME_BLT)

		*attr |= TSI148_LCSR_DDAT_TM_BLT;

	}

	if (cycle & VME_MBLT) {



	if (cycle & VME_MBLT)

		*attr |= TSI148_LCSR_DDAT_TM_MBLT;

	}

	if (cycle & VME_2eVME) {



	if (cycle & VME_2eVME)

		*attr |= TSI148_LCSR_DDAT_TM_2eVME;

	}

	if (cycle & VME_2eSST) {



	if (cycle & VME_2eSST)

		*attr |= TSI148_LCSR_DDAT_TM_2eSST;

	}



	if (cycle & VME_2eSSTB) {

		dev_err(dev, "Currently not setting Broadcast Select "

			"Registers\n");
@@ -1645,8 +1624,7 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, 
	tsi148_bridge = list->parent->parent;



	/* Descriptor must be aligned on 64-bit boundaries */

	entry = (struct tsi148_dma_entry *)kmalloc(

		sizeof(struct tsi148_dma_entry), GFP_KERNEL);

	entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);

	if (entry == NULL) {

		dev_err(tsi148_bridge->parent, "Failed to allocate memory for "

			"dma resource structure\n");
@@ -1676,13 +1654,13 @@ int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src, 
		entry->descriptor.dsal = pattern_attr->pattern;

		entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;

		/* Default behaviour is 32 bit pattern */

		if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {

		if (pattern_attr->type & VME_DMA_PATTERN_BYTE)

			entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;

		}



		/* It seems that the default behaviour is to increment */

		if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {

		if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)

			entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;

		}



		break;

	case VME_DMA_PCI:

		pci_attr = (struct vme_dma_pci *)src->private;
@@ -1896,7 +1874,7 @@ int tsi148_dma_list_empty(struct vme_dma_list *list) 
		kfree(entry);

	}



	return (0);

	return 0;

}



/*
@@ -1992,18 +1970,18 @@ int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, 
	if (lm_ctl & TSI148_LCSR_LMAT_EN)

		enabled = 1;



	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {

	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)

		*aspace |= VME_A16;

	}

	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {



	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)

		*aspace |= VME_A24;

	}

	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {



	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)

		*aspace |= VME_A32;

	}

	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {



	if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)

		*aspace |= VME_A64;

	}





	if (lm_ctl & TSI148_LCSR_LMAT_SUPR)

		*cycle |= VME_SUPER;
@@ -2252,8 +2230,7 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	/* If we want to support more than one of each bridge, we need to

	 * dynamically generate this so we get one per device

	 */

	tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),

		GFP_KERNEL);

	tsi148_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);

	if (tsi148_bridge == NULL) {

		dev_err(&pdev->dev, "Failed to allocate memory for device "

			"structure\n");
@@ -2359,8 +2336,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	/* Add master windows to list */

	INIT_LIST_HEAD(&(tsi148_bridge->master_resources));

	for (i = 0; i < master_num; i++) {

		master_image = (struct vme_master_resource *)kmalloc(

			sizeof(struct vme_master_resource), GFP_KERNEL);

		master_image = kmalloc(sizeof(struct vme_master_resource),

			GFP_KERNEL);

		if (master_image == NULL) {

			dev_err(&pdev->dev, "Failed to allocate memory for "

			"master resource structure\n");
@@ -2388,8 +2365,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	/* Add slave windows to list */

	INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));

	for (i = 0; i < TSI148_MAX_SLAVE; i++) {

		slave_image = (struct vme_slave_resource *)kmalloc(

			sizeof(struct vme_slave_resource), GFP_KERNEL);

		slave_image = kmalloc(sizeof(struct vme_slave_resource),

			GFP_KERNEL);

		if (slave_image == NULL) {

			dev_err(&pdev->dev, "Failed to allocate memory for "

			"slave resource structure\n");
@@ -2414,8 +2391,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	/* Add dma engines to list */

	INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));

	for (i = 0; i < TSI148_MAX_DMA; i++) {

		dma_ctrlr = (struct vme_dma_resource *)kmalloc(

			sizeof(struct vme_dma_resource), GFP_KERNEL);

		dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),

			GFP_KERNEL);

		if (dma_ctrlr == NULL) {

			dev_err(&pdev->dev, "Failed to allocate memory for "

			"dma resource structure\n");
@@ -2531,7 +2508,8 @@ static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
err_master:

	/* resources are stored in link list */

	list_for_each(pos, &(tsi148_bridge->master_resources)) {

		master_image = list_entry(pos, struct vme_master_resource,				list);

		master_image = list_entry(pos, struct vme_master_resource,

			list);

		list_del(pos);

		kfree(master_image);

	}

drivers/staging/vme/bridges/vme_tsi148.h

+16 −10
Original line number Diff line number Diff line
@@ -615,7 +615,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, 
 */

#define TSI148_PCFS_PCIXSTAT_RSCEM     (1<<29)	/* Recieved Split Comp Error */

#define TSI148_PCFS_PCIXSTAT_DMCRS_M   (7<<26)	/* max Cumulative Read Size */

#define TSI148_PCFS_PCIXSTAT_DMOST_M   (7<<23)	/* max outstanding Split Trans */

#define TSI148_PCFS_PCIXSTAT_DMOST_M   (7<<23)	/* max outstanding Split Trans

						 */

#define TSI148_PCFS_PCIXSTAT_DMMRC_M   (3<<21)	/* max mem read byte count */

#define TSI148_PCFS_PCIXSTAT_DC        (1<<20)	/* Device Complexity */

#define TSI148_PCFS_PCIXSTAT_USC       (1<<19)	/* Unexpected Split comp */
@@ -703,7 +704,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, 


#define TSI148_LCSR_VMCTRL_RMWEN       (1<<20)	/* RMW Enable */



#define TSI148_LCSR_VMCTRL_ATO_M       (7<<16)	/* Master Access Time-out Mask */

#define TSI148_LCSR_VMCTRL_ATO_M       (7<<16)	/* Master Access Time-out Mask

						 */

#define TSI148_LCSR_VMCTRL_ATO_32      (0<<16)	/* 32 us */

#define TSI148_LCSR_VMCTRL_ATO_128     (1<<16)	/* 128 us */

#define TSI148_LCSR_VMCTRL_ATO_512     (2<<16)	/* 512 us */
@@ -733,14 +735,16 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, 
#define TSI148_LCSR_VMCTRL_VTON_256    (6<<8)	/* 256us */

#define TSI148_LCSR_VMCTRL_VTON_512    (7<<8)	/* 512us */



#define TSI148_LCSR_VMCTRL_VREL_M      (3<<3)	/* VMEbus Master Rel Mode Mask */

#define TSI148_LCSR_VMCTRL_VREL_M      (3<<3)	/* VMEbus Master Rel Mode Mask

						 */

#define TSI148_LCSR_VMCTRL_VREL_T_D    (0<<3)	/* Time on or Done */

#define TSI148_LCSR_VMCTRL_VREL_T_R_D  (1<<3)	/* Time on and REQ or Done */

#define TSI148_LCSR_VMCTRL_VREL_T_B_D  (2<<3)	/* Time on and BCLR or Done */

#define TSI148_LCSR_VMCTRL_VREL_T_D_R  (3<<3)	/* Time on or Done and REQ */



#define TSI148_LCSR_VMCTRL_VFAIR       (1<<2)	/* VMEbus Master Fair Mode */

#define TSI148_LCSR_VMCTRL_VREQL_M     (3<<0)	/* VMEbus Master Req Level Mask */

#define TSI148_LCSR_VMCTRL_VREQL_M     (3<<0)	/* VMEbus Master Req Level Mask

						 */



/*

 *  VMEbus Control Register CRG+$238
@@ -762,7 +766,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, 
#define TSI148_LCSR_VCTRL_DLT_16384    (0xB<<24)	/* 16384 VCLKS */

#define TSI148_LCSR_VCTRL_DLT_32768    (0xC<<24)	/* 32768 VCLKS */



#define TSI148_LCSR_VCTRL_NERBB        (1<<20)	/* No Early Release of Bus Busy */

#define TSI148_LCSR_VCTRL_NERBB        (1<<20)	/* No Early Release of Bus Busy

						 */



#define TSI148_LCSR_VCTRL_SRESET       (1<<17)	/* System Reset */

#define TSI148_LCSR_VCTRL_LRESET       (1<<16)	/* Local Reset */
@@ -773,7 +778,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, 
#define TSI148_LCSR_VCTRL_ATOEN        (1<<7)	/* Arbiter Time-out Enable */

#define TSI148_LCSR_VCTRL_ROBIN        (1<<6)	/* VMEbus Round Robin */



#define TSI148_LCSR_VCTRL_GTO_M        (7<<0)	/* VMEbus Global Time-out Mask */

#define TSI148_LCSR_VCTRL_GTO_M        (7<<0)	/* VMEbus Global Time-out Mask

						 */

#define TSI148_LCSR_VCTRL_GTO_8	      (0<<0)	/* 8 us */

#define TSI148_LCSR_VCTRL_GTO_16	      (1<<0)	/* 16 us */

#define TSI148_LCSR_VCTRL_GTO_32	      (2<<0)	/* 32 us */