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Commit 793acf87 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Marc Zyngier
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arm64: KVM: Describe data or unified caches as having 1 set and 1 way 



On SMP ARM systems, cache maintenance by set/way should only ever be
done in the context of onlining or offlining CPUs, which is typically
done by bare metal firmware and never in a virtual machine. For this
reason, we trap set/way cache maintenance operations and replace them
with conditional flushing of the entire guest address space.

Due to this trapping, the set/way arguments passed into the set/way
ops are completely ignored, and thus irrelevant. This also means that
the set/way geometry is equally irrelevant, and we can simply report
it as 1 set and 1 way, so that legacy 32-bit ARM system software (i.e.,
the kind that only receives odd fixes) doesn't take a performance hit
due to the trapping when iterating over the cachelines.

Acked-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent f7f2b15c

arch/arm64/include/asm/kvm_emulate.h

+2 −1
Original line number Diff line number Diff line
@@ -78,7 +78,8 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 
	if (!vcpu_el1_is_32bit(vcpu))

		vcpu->arch.hcr_el2 |= HCR_TID3;



	if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE))

	if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||

	    vcpu_el1_is_32bit(vcpu))

		vcpu->arch.hcr_el2 |= HCR_TID2;

}

arch/arm64/kvm/sys_regs.c

+15 −0
Original line number Diff line number Diff line
@@ -1186,6 +1186,21 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 


	csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);

	p->regval = get_ccsidr(csselr);



	/*

	 * Guests should not be doing cache operations by set/way at all, and

	 * for this reason, we trap them and attempt to infer the intent, so

	 * that we can flush the entire guest's address space at the appropriate

	 * time.

	 * To prevent this trapping from causing performance problems, let's

	 * expose the geometry of all data and unified caches (which are

	 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.

	 * [If guests should attempt to infer aliasing properties from the

	 * geometry (which is not permitted by the architecture), they would

	 * only do so for virtually indexed caches.]

	 */

	if (!(csselr & 1)) // data or unified cache

		p->regval &= ~GENMASK(27, 3);

	return true;

}