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Commit 78f86013 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The interrupt departement delivers this time:

   - New infrastructure to manage NMIs on platforms which have a sane
     NMI delivery, i.e. identifiable NMI vectors instead of a single
     lump.

   - Simplification of the interrupt affinity management so drivers
     don't have to implement ugly loops around the PCI/MSI enablement.

   - Speedup for interrupt statistics in /proc/stat

   - Provide a function to retrieve the default irq domain

   - A new interrupt controller for the Loongson LS1X platform

   - Affinity support for the SiFive PLIC

   - Better support for the iMX irqsteer driver

   - NUMA aware memory allocations for GICv3

   - The usual small fixes, improvements and cleanups all over the
     place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (36 commits)
  irqchip/imx-irqsteer: Add multi output interrupts support
  irqchip/imx-irqsteer: Change to use reg_num instead of irq_group
  dt-bindings: irq: imx-irqsteer: Add multi output interrupts support
  dt-binding: irq: imx-irqsteer: Use irq number instead of group number
  irqchip/brcmstb-l2: Use _irqsave locking variants in non-interrupt code
  irqchip/gicv3-its: Use NUMA aware memory allocation for ITS tables
  irqdomain: Allow the default irq domain to be retrieved
  irqchip/sifive-plic: Implement irq_set_affinity() for SMP host
  irqchip/sifive-plic: Differentiate between PLIC handler and context
  irqchip/sifive-plic: Add warning in plic_init() if handler already present
  irqchip/sifive-plic: Pre-compute context hart base and enable base
  PCI/MSI: Remove obsolete sanity checks for multiple interrupt sets
  genirq/affinity: Remove the leftovers of the original set support
  nvme-pci: Simplify interrupt allocation
  genirq/affinity: Add new callback for (re)calculating interrupt sets
  genirq/affinity: Store interrupt sets size in struct irq_affinity
  genirq/affinity: Code consolidation
  irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.
  irqchip/i8259: Fix shutdown order by moving syscore_ops registration
  dt-bindings: interrupt-controller: loongson ls1x intc
  ...
parents 18483190 a324ca9c

Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt

+6 −5
Original line number Diff line number Diff line
@@ -6,8 +6,9 @@ Required properties: 
	- "fsl,imx8m-irqsteer"

	- "fsl,imx-irqsteer"

- reg: Physical base address and size of registers.

- interrupts: Should contain the parent interrupt line used to multiplex the

  input interrupts.

- interrupts: Should contain the up to 8 parent interrupt lines used to

  multiplex the input interrupts. They should be specified sequentially

  from output 0 to 7.

- clocks: Should contain one clock for entry in clock-names

  see Documentation/devicetree/bindings/clock/clock-bindings.txt

- clock-names:
@@ -16,8 +17,8 @@ Required properties: 
- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value must be 1.

- fsl,channel: The output channel that all input IRQs should be steered into.

- fsl,irq-groups: Number of IRQ groups managed by this controller instance.

  Each group manages 64 input interrupts.

- fsl,num-irqs: Number of input interrupts of this channel.

  Should be multiple of 32 input interrupts and up to 512 interrupts.



Example:
@@ -28,7 +29,7 @@ Example: 
		clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;

		clock-names = "ipg";

		fsl,channel = <0>;

		fsl,irq-groups = <1>;

		fsl,num-irqs = <64>;

		interrupt-controller;

		#interrupt-cells = <1>;

	};

Documentation/devicetree/bindings/interrupt-controller/loongson,ls1x-intc.txt

0 → 100644
+24 −0
Original line number Diff line number Diff line 
Loongson ls1x Interrupt Controller



Required properties:



- compatible : should be "loongson,ls1x-intc". Valid strings are:



- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 2.

- interrupts : Specifies the CPU interrupt the controller is connected to.



Example:



intc: interrupt-controller@1fd01040 {

	compatible = "loongson,ls1x-intc";

	reg = <0x1fd01040 0x18>;



	interrupt-controller;

	#interrupt-cells = <2>;



	interrupt-parent = <&cpu_intc>;

	interrupts = <2>;

};

drivers/irqchip/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -406,6 +406,15 @@ config IMX_IRQSTEER 
	help

	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.



config LS1X_IRQ

	bool "Loongson-1 Interrupt Controller"

	depends on MACH_LOONGSON32

	default y

	select IRQ_DOMAIN

	select GENERIC_IRQ_CHIP

	help

	  Support for the Loongson-1 platform Interrupt Controller.



endmenu



config SIFIVE_PLIC

drivers/irqchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -94,3 +94,4 @@ obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o 
obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o

obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o

obj-$(CONFIG_MADERA_IRQ)		+= irq-madera.o

obj-$(CONFIG_LS1X_IRQ)			+= irq-ls1x.o

drivers/irqchip/irq-brcmstb-l2.c

+6 −4
Original line number Diff line number Diff line
@@ -129,8 +129,9 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d) 
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	struct brcmstb_l2_intc_data *b = gc->private;

	unsigned long flags;



	irq_gc_lock(gc);

	irq_gc_lock_irqsave(gc, flags);

	/* Save the current mask */

	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
@@ -139,7 +140,7 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d) 
		irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);

		irq_reg_writel(gc, gc->wake_active, ct->regs.enable);

	}

	irq_gc_unlock(gc);

	irq_gc_unlock_irqrestore(gc, flags);

}



static void brcmstb_l2_intc_resume(struct irq_data *d)
@@ -147,8 +148,9 @@ static void brcmstb_l2_intc_resume(struct irq_data *d) 
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);

	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	struct brcmstb_l2_intc_data *b = gc->private;

	unsigned long flags;



	irq_gc_lock(gc);

	irq_gc_lock_irqsave(gc, flags);

	if (ct->chip.irq_ack) {

		/* Clear unmasked non-wakeup interrupts */

		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
@@ -158,7 +160,7 @@ static void brcmstb_l2_intc_resume(struct irq_data *d) 
	/* Restore the saved mask */

	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);

	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);

	irq_gc_unlock(gc);

	irq_gc_unlock_irqrestore(gc, flags);

}



static int __init brcmstb_l2_intc_of_init(struct device_node *np,